Datasheet AD5383 (Analog Devices) - 24

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Data Sheet AD5383 ON-CHIP SPECIAL FUNCTION REGISTERS (SFR) Soft CLR
The AD5383 contains a number of special function registers REG1 = REG0 = 0, A4 to A0 = 00010 (SFRs), as outlined in Table 13. SFRs are addressed with DB11 to DB0 = don’t care REG1 = REG0 = 0 and are decoded using Address Bit A4 to Executing this instruction performs the CLR, which is functionally Address Bit A0. the same as that provided by the external CLR pin. The DAC
Table 13. SFR Register Functions (REG1 = 0, REG0 = 0)
outputs are loaded with the data in the CLR code register. It takes 35 µs to fully execute the SOFT CLR, as indicated by the
R/W A4 A3 A2 A1 A0 Function
BUSY low time. X 0 0 0 0 0 NOP (No Operation) 0 0 0 0 0 1 Write CLR Code
Soft Power-Down
0 0 0 0 1 0 Soft CLR REG1 = REG0 = 0, A4 to A0 = 01000 0 0 1 0 0 0 Soft Power-Down DB11 to DB0 = don’t care 0 0 1 0 0 1 Soft Power-Up Executing this instruction performs a global power-down 0 0 1 1 0 0 Control Register Write feature that puts al channels into a low power mode that 1 0 1 1 0 0 Control Register Read reduces the analog supply current to 2 µA max, and the digital 0 0 1 0 1 0 Channel Monitor current to 20 µA. In power-down mode, the output amplifier 0 0 1 1 1 1 Soft Reset can be configured as a high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are
SFR COMMANDS
retained in power-down mode. No register can be written to
NOP (No Operation)
while in power-down. REG1 = REG0 = 0, A4 to A0 = 00000
Soft Power-Up
Performs no operation but is useful in serial readback mode to REG1 = REG0 = 0, A4 to A0 = 01001 clock out data on DOUT for diagnostic purposes. BUSY pulses DB11 to DB0 = don’t care low during a NOP operation. This instruction is used to power up the output amplifiers and
Write CLR Code
the internal reference. The time to exit power-down is 8 µs. The REG1 = REG0 = 0, A4 to A0 = 00001 hardware power-down and software function are internally DB11 to DB0 = contain the CLR data combined in a digital OR function. Bringing the CLR line low or exercising the soft clear function
Soft RESET
loads the contents of the DAC registers with the data contained REG1 = REG0 = 0, A4 to A0 = 01111 in the user configurable CLR register, and sets V DB11 to DB0 = don’t care OUT0 to VOUT31 accordingly. This can be very useful for setting up a specific This instruction is used to implement a software reset. Al output voltage in a clear condition. It is also beneficial for internal registers are reset to their default values, which calibration purposes; the user can load full scale or zero scale to correspond to m at ful -scale and c at zero scale. The contents of the clear code register and then issue a hardware or software the DAC registers are cleared, setting all analog outputs to 0 V. clear to load this code to all DACs, removing the need for The soft reset activation time is 135 µs. Only perform a soft individual writes to each DAC. Default on power-up is all zeros. reset when the AD5383 is not in power-down mode. Rev. D | Page 23 of 40 Document Outline Features Integrated Functions Applications Functional Block Diagram Table of Contents Revision History General Description Specifications AD5383-5 Specifications AD5383-3 Specifications AC Characteristics9F Timing Characteristics Serial Interface Timing I2C Serial Interface Timing Parallel Interface Timing Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Functional Description DAC Architecture—General Data Decoding On-Chip Special Function Registers (SFR) SFR Commands NOP (No Operation) Write CLR Code Soft CLR Soft Power-Down Soft Power-Up Soft RESET Control Register Write/Read Channel Monitor Function Hardware Functions Reset Function Asynchronous Clear Function BUSY\ and LDAC\ Functions FIFO Operation in Parallel Mode Power-On Reset Power-Down Interfaces DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces Standalone Mode Daisy-Chain Mode Readback Mode I2C Serial Interface I2C Data Transfer START and STOP Conditions Repeated START Conditions Acknowledge Bit (ACK) AD5383 Slave Addresses Write Operation 4-Byte Mode 3-Byte Mode 2-Byte Mode Parallel Interface CS\ Pin WR\ Pin REG0, REG1 Pins Pins A4 to A0 Pins DB11 to DB0 Microprocessor Interfacing Parallel Interface AD5383 to MC68HC11 AD5383 to PIC16C6x/7x AD5383 to 8051 AD5383 to ADSP-BF527 Applications Information Power Supply Decoupling Power Supply Sequencing Typical Configuration Circuit Channel Monitor Function Toggle Mode Function Thermal Monitor Function Optical Attenuators Utilizing the FIFO Outline Dimensions Ordering Guide