Datasheet LTC6906 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Micropower, 10kHz to 1MHz Resistor Set Oscillator in SOT-23 |
| Pages / Page | 14 / 5 — PIN FUNCTIONS. OUT (Pin 1):. GND (Pin 2):. DIV (Pin 3):. GRD (Pin 5):. V+ … |
| File Format / Size | PDF / 172 Kb |
| Document Language | English |
PIN FUNCTIONS. OUT (Pin 1):. GND (Pin 2):. DIV (Pin 3):. GRD (Pin 5):. V+ (Pin 6):. SET (Pin 4):. BLOCK DIAGRAM
Model Line for this Datasheet
Text Version of Document
LTC6906
PIN FUNCTIONS OUT (Pin 1):
Oscillator Output. The OUT pin swings from or better temperature coefficient. For lower accu racy ap- GND to V+ with an output resis tance of approximately plications, an inexpensive 1% thick-film resistor may be 150Ω. For micropower operation, the load re sistance must used. Limit the capacitance in parallel with RSET to less be kept as high as possible and the load capacitance as than 10pF to reduce jitter and to ensure stability. Capaci- low as possible. tance greater than 10pF could cause the LTC6906 internal feedback circuits to oscillate. The volt age on the SET pin
GND (Pin 2):
Ground. is approximately 650mV and decreases with temperature
DIV (Pin 3):
Divider Setting Input. This three-level input by about –2.2mV/°C. selects one of three internal digital divider settings, de-
GRD (Pin 5):
Guard Signal. This pin can be used to reduce termining the value of N in the frequency equation. Tie to PC board leakage across the frequency setting resistor, GND for ÷1, leave floating for ÷3 and tie to V+ for ÷10. R When left floating, the LTC6906 pulls Pin 3 to mid-supply SET. The GRD pin is held within a few millivolts of the SET pin and shunts leakage current away from the SET pin. with a 2.5M resistor. When Pin 3 is floating, care should To control leakage, connect a bare copper trace (a trace be taken to reduce coupling from the OUT pin and its with no solder mask) to GRD and loop it around the SET trace to Pin 3. Coupling can be reduced by increasing the pin and all PC board metal connected to SET. physical space between traces or by shielding the DIV pin with grounded metal.
V+ (Pin 6):
Voltage Supply (2.25V to 3.6V). This supply is internally decoupled with a 20Ω resistor in series with
SET (Pin 4):
Frequency Setting Resistor Input. Connect an 800pF capacitor. No external decoupling capacitor is a resistor, RSET, from this pin to GND to set the oscillator required for OUT pin loads less than 50pF. V+ should be frequency. For best perform ance use a precision metal- or kept reasonably free of noise and ripple. thin-film resistor of 0.5% or better tolerance and 50ppm/°C
BLOCK DIAGRAM
DECOUPLING NETWORK V+ FREQUENCY-TO-CURRENT CONVERTERS V+ 20 5M 6 fOSC THREE-LEVEL 800pF DIV INPUT 3 GND 2 I I FB FB DETECTOR 5M DIVIDER VSET VGRD 650mV SELECT ISET = IFB VSET SET VSET – f 4 OSC 150Ω DRIVER VOLTAGE PROGRAMMABLE CONTROLLED OUT BUFFER OP AMP DIVIDER (n) 1 RSET GRD VSET + OSCILLATOR (1, 3, 10) 5 (MASTER OSCILLATOR) fOSC.)[tLĀ3SET 6906 BD 6906fc 5
PIN FUNCTIONS OUT (Pin 1):
Oscillator Output. The OUT pin swings from or better temperature coefficient. For lower accu racy ap- GND to V+ with an output resis tance of approximately plications, an inexpensive 1% thick-film resistor may be 150Ω. For micropower operation, the load re sistance must used. Limit the capacitance in parallel with RSET to less be kept as high as possible and the load capacitance as than 10pF to reduce jitter and to ensure stability. Capaci- low as possible. tance greater than 10pF could cause the LTC6906 internal feedback circuits to oscillate. The volt age on the SET pin
GND (Pin 2):
Ground. is approximately 650mV and decreases with temperature
DIV (Pin 3):
Divider Setting Input. This three-level input by about –2.2mV/°C. selects one of three internal digital divider settings, de-
GRD (Pin 5):
Guard Signal. This pin can be used to reduce termining the value of N in the frequency equation. Tie to PC board leakage across the frequency setting resistor, GND for ÷1, leave floating for ÷3 and tie to V+ for ÷10. R When left floating, the LTC6906 pulls Pin 3 to mid-supply SET. The GRD pin is held within a few millivolts of the SET pin and shunts leakage current away from the SET pin. with a 2.5M resistor. When Pin 3 is floating, care should To control leakage, connect a bare copper trace (a trace be taken to reduce coupling from the OUT pin and its with no solder mask) to GRD and loop it around the SET trace to Pin 3. Coupling can be reduced by increasing the pin and all PC board metal connected to SET. physical space between traces or by shielding the DIV pin with grounded metal.
V+ (Pin 6):
Voltage Supply (2.25V to 3.6V). This supply is internally decoupled with a 20Ω resistor in series with
SET (Pin 4):
Frequency Setting Resistor Input. Connect an 800pF capacitor. No external decoupling capacitor is a resistor, RSET, from this pin to GND to set the oscillator required for OUT pin loads less than 50pF. V+ should be frequency. For best perform ance use a precision metal- or kept reasonably free of noise and ripple. thin-film resistor of 0.5% or better tolerance and 50ppm/°C
BLOCK DIAGRAM
DECOUPLING NETWORK V+ FREQUENCY-TO-CURRENT CONVERTERS V+ 20 5M 6 fOSC THREE-LEVEL 800pF DIV INPUT 3 GND 2 I I FB FB DETECTOR 5M DIVIDER VSET VGRD 650mV SELECT ISET = IFB VSET SET VSET – f 4 OSC 150Ω DRIVER VOLTAGE PROGRAMMABLE CONTROLLED OUT BUFFER OP AMP DIVIDER (n) 1 RSET GRD VSET + OSCILLATOR (1, 3, 10) 5 (MASTER OSCILLATOR) fOSC.)[tLĀ3SET 6906 BD 6906fc 5
