Datasheet Datasheet ATtiny24A, ATtiny44A, ATtiny84A. Summary (Microchip) - 4
| Manufacturer | Microchip |
| Description | 8-bit Microcontroller with 2K/4K/8K Bytes In-System Programmable Flash |
| Pages / Page | 22 / 4 — Overview. Figure 2-1. ATtiny24A/44A/84A |
| File Format / Size | PDF / 707 Kb |
| Document Language | English |
Overview. Figure 2-1. ATtiny24A/44A/84A
Model Line for this Datasheet
- ATTINY24A-CCU ATTINY24A-CCUR ATTINY24A-MF ATTINY24A-MFR ATTINY24A-MM8 ATTINY24A-MM8R ATTINY24A-MMH ATTINY24A-MMHR ATTINY24A-MU ATTINY24A-MUR ATTINY24A-PU ATTINY24A-SSF ATTINY24A-SSFR ATTINY24A-SSN ATTINY24A-SSNR ATTINY24A-SSU ATTINY24A-SSUR
Text Version of Document
2. Overview
ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful in structions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1.
Block Diagram VCC 8-BIT DATABUS INTERNAL INTERNAL CALIBRATED OSCILLATOR OSCILLATOR GND PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL PROGRAM SRAM REGISTER FLASH MCU STATUS INSTRUCTION GENERAL REGISTER REGISTER PURPOSE REGISTERS TIMER/ X COUNTER0 INSTRUCTION Y DECODER Z TIMER/ COUNTER1 CONTROL ALU LINES STATUS REGISTER INTERRUPT UNIT PROGRAMMING EEPROM LOGIC ISP INTERFACE OSCILLATORS R O T DATA REGISTER DATA DIR. ADC DATA REGISTER DATA DIR. + _ PORT A REG.PORT A PORT B REG.PORT B ARA ANALOG COMP PORT A DRIVERS PORT B DRIVERS PA[7:0] PB[3:0] The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers.
4 ATtiny24A/44A/84A
8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08
ATtiny24A/44A/84A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful in structions in a single clock cycle, the ATtiny24A/44A/84A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1.
Block Diagram VCC 8-BIT DATABUS INTERNAL INTERNAL CALIBRATED OSCILLATOR OSCILLATOR GND PROGRAM STACK WATCHDOG TIMING AND COUNTER POINTER TIMER CONTROL MCU CONTROL PROGRAM SRAM REGISTER FLASH MCU STATUS INSTRUCTION GENERAL REGISTER REGISTER PURPOSE REGISTERS TIMER/ X COUNTER0 INSTRUCTION Y DECODER Z TIMER/ COUNTER1 CONTROL ALU LINES STATUS REGISTER INTERRUPT UNIT PROGRAMMING EEPROM LOGIC ISP INTERFACE OSCILLATORS R O T DATA REGISTER DATA DIR. ADC DATA REGISTER DATA DIR. + _ PORT A REG.PORT A PORT B REG.PORT B ARA ANALOG COMP PORT A DRIVERS PORT B DRIVERS PA[7:0] PB[3:0] The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers.
4 ATtiny24A/44A/84A
8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08
