Datasheet Datasheet ATtiny24A, ATtiny44A, ATtiny84A. Summary (Microchip) - 5
| Manufacturer | Microchip |
| Description | 8-bit Microcontroller with 2K/4K/8K Bytes In-System Programmable Flash |
| Pages / Page | 22 / 5 — ATtiny24A/44A/84A |
| File Format / Size | PDF / 707 Kb |
| Document Language | English |
ATtiny24A/44A/84A
Model Line for this Datasheet
- ATTINY24A-CCU ATTINY24A-CCUR ATTINY24A-MF ATTINY24A-MFR ATTINY24A-MM8 ATTINY24A-MM8R ATTINY24A-MMH ATTINY24A-MMHR ATTINY24A-MU ATTINY24A-MUR ATTINY24A-PU ATTINY24A-SSF ATTINY24A-SSFR ATTINY24A-SSN ATTINY24A-SSNR ATTINY24A-SSU ATTINY24A-SSUR
Text Version of Document
ATtiny24A/44A/84A
The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Program- mable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software select- able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O mod- ules except the ADC. In Power-down mode registers keep their contents and all chip functions are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The ATtiny24A/44A/84A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
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8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08
The ATtiny24A/44A/84A provides the following features: 2K/4K/8K byte of In-System Program- mable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software select- able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O mod- ules except the ADC. In Power-down mode registers keep their contents and all chip functions are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The on- chip ISP Flash allows the Program memory to be re-programmed in-system through an SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code running on the AVR core. The ATtiny24A/44A/84A AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
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8183FS–AVR–06/12 Document Outline Features 1. Pin Configurations 1.1 Pin Descriptions 1.1.1 VCC 1.1.2 GND 1.1.3 Port B (PB3:PB0) 1.1.4 RESET 1.1.5 Port A (PA7:PA0) 2. Overview 3. General Information 3.1 Resources 3.2 Code Examples 3.3 Capacitive Touch Sensing 3.4 Data Retention 3.5 Disclaimer 4. Register Summary 5. Instruction Set Summary 6. Ordering Information 6.1 ATtiny24A 6.2 ATtiny44A 6.3 ATtiny84A 7. Packaging Information 7.1 14S1 7.2 14P3 7.3 15CC1 7.4 20M1 7.5 20M2 8. Errata 8.1 ATtiny24A 8.1.1 Rev. H 8.1.2 Rev. G 8.1.3 Rev. F 8.2 ATtiny44A 8.2.1 Rev. G 8.2.2 Rev. F 8.2.3 Rev. E 8.3 ATtiny84A 8.3.1 Rev. C 9. Datasheet Revision History 9.1 Rev. 8183F – 06/12 9.2 Rev. 8183E – 01/12 9.3 Rev. 8183D – 04/11 9.4 Rev. 8183C – 03/11 9.5 Rev. 8183B – 03/10 9.6 Rev. 8183A – 12/08
