Datasheet ADIS16137 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | ±1000°/Sec Precision Angular Rate Sensor |
| Pages / Page | 21 / 5 — ADIS16137. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. … |
| Revision | A |
| File Format / Size | PDF / 521 Kb |
| Document Language | English |
ADIS16137. Data Sheet. TIMING SPECIFICATIONS. Table 2. Normal Mode. Parameter. Description. Min1. Typ. Max. Unit. Timing Diagrams. tCS. tSFS. SCLK
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ADIS16137 Data Sheet TIMING SPECIFICATIONS
TA = 25°C, VDD = 5 V, unless otherwise noted.
Table 2. Normal Mode Parameter Description Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.5 MHz tSTALL Stall period between data, see Figure 3 15 µs tREADRATE Read rate 25 µs tCS Chip select to clock edge 48.8 ns tDAV DOUT valid after SCLK edge 25 ns tDSU DIN setup time before SCLK rising edge 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 ns tSCLKR, tSCLKF SCLK rise and fall times, not shown in figures 5 12.5 ns tDR, tDF DOUT rise and fall times, not shown in figures 5 12.5 ns tSFS CS high after SCLK edge 0 ns t1 Input sync positive pulse width 5 µs t2 Input sync to data ready output 300 µs t3 Input sync period 488 µs tx Input sync low time 100 µs 1 Guaranteed by design and characterization but not tested in production.
Timing Diagrams CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 11854- Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS
003
SCLK
11854- Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (CLKIN)
004
DATA READY
1854- 1 Figure 4. Input Clock Timing Diagram Rev. A | Page 4 of 20 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Reading Sensor Data Output Data Registers Rotation Rate (Gyroscope) Internal Temperature Device Configuration Dual Memory Structure User Registers Digital Processing Configuration Internal Sample Rate Input Clock Configuration Digital Filtering Averaging/Decimation Filter Calibration Automatic Bias Correction (Autonull) Manual Bias Correction Restoring Factory Calibration Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example System Controls Global Commands Software Reset Memory Management Checksum Test General-Purpose Input/Output Data Ready Input/Output Indicator Example Input/Output Configuration Automatic Self Test Power Management Status Product Identification Applications Information Power Supply Considerations Prototype Interface Board Installation Tips Packaging and Ordering Information Outline Dimensions Ordering Guide
ADIS16137 Data Sheet TIMING SPECIFICATIONS
TA = 25°C, VDD = 5 V, unless otherwise noted.
Table 2. Normal Mode Parameter Description Min1 Typ Max Unit
fSCLK Serial clock 0.01 2.5 MHz tSTALL Stall period between data, see Figure 3 15 µs tREADRATE Read rate 25 µs tCS Chip select to clock edge 48.8 ns tDAV DOUT valid after SCLK edge 25 ns tDSU DIN setup time before SCLK rising edge 24.4 ns tDHD DIN hold time after SCLK rising edge 48.8 ns tSCLKR, tSCLKF SCLK rise and fall times, not shown in figures 5 12.5 ns tDR, tDF DOUT rise and fall times, not shown in figures 5 12.5 ns tSFS CS high after SCLK edge 0 ns t1 Input sync positive pulse width 5 µs t2 Input sync to data ready output 300 µs t3 Input sync period 488 µs tx Input sync low time 100 µs 1 Guaranteed by design and characterization but not tested in production.
Timing Diagrams CS tCS tSFS 1 2 3 4 5 6 15 16 SCLK tDAV DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB t t DSU DHD DIN R/W A6 A5 A4 A3 A2 D2 D1 LSB
002 11854- Figure 2. SPI Timing and Sequence
tREADRATE tSTALL CS
003
SCLK
11854- Figure 3. Stall Time and Data Rate
t3 t2 t t 1 X SYNC CLOCK (CLKIN)
004
DATA READY
1854- 1 Figure 4. Input Clock Timing Diagram Rev. A | Page 4 of 20 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Reading Sensor Data Output Data Registers Rotation Rate (Gyroscope) Internal Temperature Device Configuration Dual Memory Structure User Registers Digital Processing Configuration Internal Sample Rate Input Clock Configuration Digital Filtering Averaging/Decimation Filter Calibration Automatic Bias Correction (Autonull) Manual Bias Correction Restoring Factory Calibration Alarms Static Alarm Use Dynamic Alarm Use Alarm Reporting Alarm Example System Controls Global Commands Software Reset Memory Management Checksum Test General-Purpose Input/Output Data Ready Input/Output Indicator Example Input/Output Configuration Automatic Self Test Power Management Status Product Identification Applications Information Power Supply Considerations Prototype Interface Board Installation Tips Packaging and Ordering Information Outline Dimensions Ordering Guide
