Datasheet KSZ8765CLX (Microchip) - 6
| Manufacturer | Microchip |
| Description | Integrated 5-Port 10/100-Managed Ethernet Switch with Gigabit GMII/RGMII and MII/ RMII Interfaces |
| Pages / Page | 131 / 6 — KSZ8765CLX. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 80-LQFP … |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
KSZ8765CLX. 2.0. PIN DESCRIPTION AND CONFIGURATION. FIGURE 2-1:. 80-LQFP PIN ASSIGNMENT (TOP VIEW). KSZ8765. (TOP VIEW)
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KSZ8765CLX 2.0 PIN DESCRIPTION AND CONFIGURATION FIGURE 2-1: 80-LQFP PIN ASSIGNMENT (TOP VIEW)
T33 TST XO XI GNDA ISET VDDA A NC VDD12D RST_N GNDD VDDIO SPIS_N SDA_MDIO SCL_MDC SPIQ LED1_0 LED1_1 LED2_0 LED2_1 GNDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD12A 1 60 RXD5_7 VDDAT33 2 59 RXD5_6 GNDA 3 58 RXD5_5 RXP1 4 57 RXD5_4 RXM1 5 56 PME TXP1 6 55 REFCLKO TXM1 7 54 COL5 RXP2 8 53 CRS5 RXM2 9
KSZ8765
52 RXER5 TXP2 10 51 RXDV5/CRSDV5/RXD5_CTL TXM2 11 50 RXD5_3
(TOP VIEW)
VDDAT33 12 49 RXD5_2 RXP3 13 48 VDDIO RXM3 14 47 GNDD TXP3 15 46 RXD5_1 TXM3 16 45 RXD5_0 RXP4 17 44 RXC5/GRXC5 RXM4 18 43 TXC5/REFCLKI5/GTXC5 TXP4 19 42 VDD12D TXM4 20 41 TXD5_7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC GNDA GNDD GNDD INTR_N LED3_1 LED3_0 VDDIO VDD12D LED4_1 TXD5_0 LED4_0 TXD5_1 TXD5_2 TXD5_3 TXER5 TXD5_4 TXD5_5 TXD5_6 TXEN5/TXDS5_CTL DS00002130A-page 6
2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
T33 TST XO XI GNDA ISET VDDA A NC VDD12D RST_N GNDD VDDIO SPIS_N SDA_MDIO SCL_MDC SPIQ LED1_0 LED1_1 LED2_0 LED2_1 GNDD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD12A 1 60 RXD5_7 VDDAT33 2 59 RXD5_6 GNDA 3 58 RXD5_5 RXP1 4 57 RXD5_4 RXM1 5 56 PME TXP1 6 55 REFCLKO TXM1 7 54 COL5 RXP2 8 53 CRS5 RXM2 9
KSZ8765
52 RXER5 TXP2 10 51 RXDV5/CRSDV5/RXD5_CTL TXM2 11 50 RXD5_3
(TOP VIEW)
VDDAT33 12 49 RXD5_2 RXP3 13 48 VDDIO RXM3 14 47 GNDD TXP3 15 46 RXD5_1 TXM3 16 45 RXD5_0 RXP4 17 44 RXC5/GRXC5 RXM4 18 43 TXC5/REFCLKI5/GTXC5 TXP4 19 42 VDD12D TXM4 20 41 TXD5_7 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC GNDA GNDD GNDD INTR_N LED3_1 LED3_0 VDDIO VDD12D LED4_1 TXD5_0 LED4_0 TXD5_1 TXD5_2 TXD5_3 TXER5 TXD5_4 TXD5_5 TXD5_6 TXEN5/TXDS5_CTL DS00002130A-page 6
2016 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
