Datasheet KSZ8794CNX (Microchip)

ManufacturerMicrochip
DescriptionIntegrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface
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KSZ8794CNX. Integrated 4-Port 10/100 Managed Ethernet. Switch with Gigabit RGMII/MII/RMII Interface. Target Applications

Datasheet KSZ8794CNX Microchip

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KSZ8794CNX Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface Target Applications
- On-Chip Termination Resistors and Internal Biasing for Differential Pairs to Reduce • Industrial Ethernet Applications that Employ IEEE Power 802.3-Compliant MACs. (Ethernet/IP, Profinet, - HP Auto MDI/MDI-X Crossover Support Elim- MODBUS TCP, etc.) inates the Need to Differentiate Between • VoIP Phone Straight or Crossover Cables in Applications • Set-Top/Game Box • MAC and GMAC Ports • Automotive - Three Internal Media Access Control (MAC1 • Industrial Control to MAC3) Units and One Internal Gigabit • IPTV POF Media Access Control (GMAC4) Unit • SOHO Residential Gateway with Full-Wire Speed - RGMII, MII, or RMII Interfaces Support for of Four LAN Ports the Port 4 GMAC4 with Uplink • Broadband Gateway/Firewall/VPN - 2 KByte Jumbo Packet Support • Integrated DSL/Cable Modem - Tail Tagging Mode (One Byte Added Before • Wireless LAN Access Point + Gateway FCS) Support on Port 4 to Inform the Proces- • Standalone 10/100 Switch sor in which Ingress Port Receives the Packet and its Priority • Networked Measurement and Control Systems - Supports Reduced Media Independent Inter- face (RMII) with 50 MHz Reference Clock
Features
Output • Management Capabilities - Supports Media Independent Interface (MII) - The KSZ8794CNX Includes All the Functions in Either PHY Mode or MAC Mode on Port 4 of a 10/100BASE-T/TX Switch System Which - LinkMD® Cable Diagnostic Capabilities for Combines a Switch Engine, Frame Buffer Determining Cable Opens, Shorts, and Management, Address Look-Up Table, Length Queue Management, MIB Counters, Media • Advanced Switch Capabilities Access Controllers (MAC), and PHY Trans- - Non-Blocking Store-and-Forward Switch ceivers Fabric Assures Fast Packet Delivery by Uti- - Non-Blocking Store-and-Forward Switch lizing a 1024-Entries Forwarding Table Fabric Assures Fast Packet Delivery by Uti- - 64 KB Frame Buffer RAM lizing a 1024-Entries Forwarding Table - IEEE 802.1q VLAN Support for up to 128 - Port Mirroring/Monitoring/Sniffing: Ingress Active VLAN Groups (Full-Range 4096 of and/or Egress Traffic to Any Port VLAN IDs) - MIB Counters for Fully Compliant Statistics - IEEE 802.1p/Q Tag Insertion or Removal on Gathering (36 Counters per Port) a Per Port Basis (Egress) - Support Hardware for Port-Based Flush and - VLAN ID Tag/Untag Options on Per Port Freeze Command in MIB Counter. Basis - Multiple Loopback of Remote PHY, and MAC - Fully Compliant with IEEE 802.3/802.3u Modes Support for the Diagnostics Standards - Rapid Spanning Tree Support (RSTP) for - IEEE 802.3x Full-Duplex with Force-Mode Topology Management and Ring/Linear Option and Half-Duplex Back-Pressure Colli- Recovery sion Flow Control • Robust PHY Ports - IEEE 802.1w Rapid Spanning Tree Protocol - Four Integrated IEEE 802.3/802.3u-Compli- Support ant Ethernet Transceivers Supporting - IGMP v1/v2/v3 Snooping for Multicast Packet 10BASE-T and 100BASE-TX Filtering - IEEE 802.1az EEE Supported  2016 Microchip Technology Inc.

DS00002134A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines