Datasheet KSZ8794CNX (Microchip) - 5
| Manufacturer | Microchip |
| Description | Integrated 4-Port 10/100 Managed Ethernet Switch with Gigabit RGMII/MII/RMII Interface |
| Pages / Page | 124 / 5 — KSZ8794CNX. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
KSZ8794CNX. 1.0. INTRODUCTION. 1.1. General Description. FIGURE 1-1:. FUNCTIONAL BLOCK DIAGRAM. KSZ8794
Model Line for this Datasheet
Text Version of Document
KSZ8794CNX 1.0 INTRODUCTION 1.1 General Description
The KSZ8794CNX is a highly integrated, Layer 2-managed, four-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports and one 10/100/ 1000 Mbps Gigabit uplink port. The KSZ8794CNX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, program- mable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet fil- tering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8794CNX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the GMAC interface can be configured to any of RGMII, MII, and RMII modes. The KSZ8794CNX is built on the latest industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline the overall design: • Three integrated 10/100BASE-T/TX MAC/PHYs. • One integrated 10/100/1000BASE-T/TX GMAC with selectable RGMII, MII, or RMII interfaces. • Small 64-pin QFN package. A robust assortment of power management features including Energy Efficient Ethernet (EEE), PME, and WoL have been designed in to satisfy energy efficient environments. All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface.
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM KSZ8794
LOOK UP ENGINE 10/100 10/100 AUTO MDI/MDIX T/TX MAC 1 EEE PHY1 FIFO, FLOW CONTROL, VLAN 10/100 10/100 QUEUE MANAGEMENT AUTO MDI/MDIX T/TX MAC 2 EEE PHY2 10/100 10/100 AUTO MDI/MDIX T/TX MAC 3 EEE PHY3 BUFFER MANAGEMENT TAGGING, PRIORITY SW4-RGMII/MII/RMII 10/100/1000 GMAC 4 FRAME BUFFER MDC, MDI/O FOR MIIM CONTROL REG SPI I/F SPI LED0 {3:1] MIB COUNTERS LED I/F CONTROL LED1 {3:1] REGISTERS 2016 Microchip Technology Inc.
DS00002134A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
The KSZ8794CNX is a highly integrated, Layer 2-managed, four-port switch with numerous features designed to reduce system cost. It is intended for cost-sensitive applications requiring three 10/100 Mbps copper ports and one 10/100/ 1000 Mbps Gigabit uplink port. The KSZ8794CNX incorporates a small package outline, lowest power consumption with internal biasing, and on-chip termination. Its extensive features set includes enhanced power management, program- mable rate limiting and priority ratio, tagged and port-based VLAN, port-based security and ACL rule-based packet fil- tering technology, QoS priority with four queues, management interfaces, enhanced MIB counters, high-performance memory bandwidth, and a shared memory-based switch fabric with non-blocking support. The KSZ8794CNX provides support for multiple CPU data interfaces to effectively address both current and emerging fast Ethernet and Gigabit Ethernet applications where the GMAC interface can be configured to any of RGMII, MII, and RMII modes. The KSZ8794CNX is built on the latest industry-leading Ethernet analog and digital technology, with features designed to offload host processing and streamline the overall design: • Three integrated 10/100BASE-T/TX MAC/PHYs. • One integrated 10/100/1000BASE-T/TX GMAC with selectable RGMII, MII, or RMII interfaces. • Small 64-pin QFN package. A robust assortment of power management features including Energy Efficient Ethernet (EEE), PME, and WoL have been designed in to satisfy energy efficient environments. All registers in the MAC and PHY units can be managed through the SPI interface. MIIM PHY registers can be accessed through the MDC/MDIO interface.
FIGURE 1-1: FUNCTIONAL BLOCK DIAGRAM KSZ8794
LOOK UP ENGINE 10/100 10/100 AUTO MDI/MDIX T/TX MAC 1 EEE PHY1 FIFO, FLOW CONTROL, VLAN 10/100 10/100 QUEUE MANAGEMENT AUTO MDI/MDIX T/TX MAC 2 EEE PHY2 10/100 10/100 AUTO MDI/MDIX T/TX MAC 3 EEE PHY3 BUFFER MANAGEMENT TAGGING, PRIORITY SW4-RGMII/MII/RMII 10/100/1000 GMAC 4 FRAME BUFFER MDC, MDI/O FOR MIIM CONTROL REG SPI I/F SPI LED0 {3:1] MIB COUNTERS LED I/F CONTROL LED1 {3:1] REGISTERS 2016 Microchip Technology Inc.
DS00002134A-page 5 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer (PHY) 3.2 Media Access Controller (MAC) Operation 3.3 Switch Core 3.4 Power and Power Management 3.5 Interfaces 3.6 Advanced Functionality 4.0 Device Registers 4.1 Register Map 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 PME Indirect Registers 4.8 ACL Rule Table and ACL Indirect Registers 4.9 EEE Indirect Registers 4.10 Management Information Base (MIB) Counters 4.11 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Diagrams 8.0 Reset Circuit 9.0 Selection of Isolation Transformer 10.0 Selection of Reference Crystal 11.0 Package Outlines
