Datasheet KS8995E (Microchip) - 4

ManufacturerMicrochip
Description5-Port 10/100 Integrated Switch with PHY and Frame Buffer
Pages / Page41 / 4 — KS8995E Micrel Table of Contents. System Level Applications . 6
File Format / SizePDF / 201 Kb
Document LanguageEnglish

KS8995E Micrel Table of Contents. System Level Applications . 6

KS8995E Micrel Table of Contents System Level Applications  6

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KS8995E Micrel Table of Contents
System Level Applications . 6
Pin Description . 7 I/O Grouping . 11 I/O Descriptions . 12
Pin Configuration . 16
Functional Overview: Physical Layer Transceiver . 17
100BaseTX Transmit . 17
100BaseTX Receive . 17
PLL Clock Synthesizer . 17
Scrambler/De-scrambler (100BaseTX only) . 17
100BaseFX operation . 17
100BaseFX Signal Detection . 17
100BaseFX Far End Fault . 17
10BaseT Transmit . 17
10BaseT Receive . 17
Power Management . 18
Power Save Mode . 18
MDI/MDI-X Auto Crossover . 18
Auto-Negotiation . 18
Functional Overview: Switch Core . 19
Address Look Up . 19
Learning . 19
Migration . 19
Aging . 19 Forwarding . 19
Switching Engine . 19
MAC (Media Access Controller) Operation . 19
Inter Packet Group . 19
Back off Algorithm . 19
Late Collision . 19
Illegal Frame . 19
Flow Control . 19
Half-Duplex Back Pressure . 19
Broadcast Storm Protection . 19
MII Interface Operation . 21
SNI Interface (7-wire) Operation . 22
8995E Improvements . 22
Priority Schemes . 22
Per Port Method . 22
802.1p Method . 22
IPv4 DSCP Method . 22
Other Priority Considerations . 22
VLAN Operations . 23
Other Programmable Features . 24
EEPROM Operations . 24
Compatibility with KS8995 . 24 KS8995E 4 August 2003
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