Datasheet ATmega163, ATmega163L - Summary (Atmel) - 5
| Manufacturer | Atmel |
| Description | 8-bit AVR Microcontroller with 16K Bytes In-System Programmable Flash. Not Recommend for New Designs. Use ATmega16 |
| Pages / Page | 18 / 5 — ATmega163(L). Port D (PD7..PD0). RESET. XTAL1. XTAL2. AVCC. AREF. AGND |
| File Format / Size | PDF / 324 Kb |
| Document Language | English |
ATmega163(L). Port D (PD7..PD0). RESET. XTAL1. XTAL2. AVCC. AREF. AGND
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Text Version of Document
ATmega163(L)
Port C also serves the functions of various special features of the ATmega163 as listed on page 124.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the ATmega163 as listed on page 128. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
AVCC
This is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be con- nected to VCC through a low-pass filter. See page 105 for details on operation of the ADC.
AREF
AREF is the analog reference input pin for the A/D Converter. For ADC operations, a voltage in the range 2.5V to AVCC can be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground plane, this pin should be con- nected to this ground plane. Otherwise, connect to GND.
5
1142ES–AVR–02/03 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 Erratas ATmega163(L) Errata Rev. F ChangeLog Changes from Rev. 1142C-09/01 to Rev. 1142D-09/02 Changes from Rev. 1142D-09/09 to Rev. 1142E-02/03
Port C also serves the functions of various special features of the ATmega163 as listed on page 124.
Port D (PD7..PD0)
Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the ATmega163 as listed on page 128. The Port D pins are tristated when a reset condition becomes active, even if the clock is not running.
RESET
Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a Reset.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
AVCC
This is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be con- nected to VCC through a low-pass filter. See page 105 for details on operation of the ADC.
AREF
AREF is the analog reference input pin for the A/D Converter. For ADC operations, a voltage in the range 2.5V to AVCC can be applied to this pin.
AGND
Analog ground. If the board has a separate analog ground plane, this pin should be con- nected to this ground plane. Otherwise, connect to GND.
5
1142ES–AVR–02/03 Document Outline Features Pin Configurations Description Block Diagram Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) RESET XTAL1 XTAL2 AVCC AREF AGND Register Summary Instruction Set Summary Ordering Information Packaging Information 44A 40P6 Erratas ATmega163(L) Errata Rev. F ChangeLog Changes from Rev. 1142C-09/01 to Rev. 1142D-09/02 Changes from Rev. 1142D-09/09 to Rev. 1142E-02/03
