Datasheet LT1027 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Precision 5 Volt Reference |
| Pages / Page | 8 / 5 — APPLICATI. S I FOR ATIO. Effect of Reference Drift on System Accuracy. … |
| File Format / Size | PDF / 220 Kb |
| Document Language | English |
APPLICATI. S I FOR ATIO. Effect of Reference Drift on System Accuracy. Transient Response. Kelvin Connections
Model Line for this Datasheet
Text Version of Document
LT1027
O U U W U APPLICATI S I FOR ATIO Effect of Reference Drift on System Accuracy
to approximately 1.2µVRMS in a 10Hz to 1kHz bandwidth. Transient response is not affected by this capacitor. Start- A large portion of the temperature drift error budget in up settling time will increase to several milliseconds due many systems is the system reference voltage. Figure 1 to the 7kΩ impedance looking into the NR pin. The indicates the maximum temperature coefficient allowable capacitor must be a low leakage type. Electrolytics are not if the reference is to contribute no more than 0.5LSB error suitable for this application. Just 100nA leakage current to the overall system performance. The example shown is will result in a 150ppm error in output voltage. This pin is a 12-bit system designed to operate over a temperature the most sensitive pin on the device. For maximum protec- range from 25°C to 65°C. Assuming the system calibra- tion a guard ring is recommended. The ring should be tion is performed at 25°C, the temperature span is 40°C. driven from a resistive divider from V It can be seen from the graph that the temperature coeffi- OUT set to 4.4V (the open-circuit voltage on the NR pin). cient of the reference must be no worse than 3ppm/°C if it is to contribute less than 0.5LSB error. For this reason,
Transient Response
the LT1027 has been optimized for low drift. The LT1027 has been optimized for transient response. 100 Settling time is under 2µs when an AC-coupled 10mA load 8-BIT transient is applied to the output. The LT1027 achieves °C) fast settling by using a class B NPN/PNP output stage. When sinking current, the device may oscillate with ca- 10-BIT 10 pacitive loads greater than 100pF. The LT1027 is stable with all capacitive loads when at no DC load or when 12-BIT sourcing current, although for best settling time either no 0.5LSB ERROR (ppm/ 14-BIT output bypass capactor or a 4.7µF tantalum unit is recom- mended. An 0.1µF ceramic output capacitor will maximize MAXIMUM TEMPERATURE COEFFICIENT FOR 1.0 0 10 20 40 50 60 70 80 90 100 output ringing and is not recommended. 30 TEMPERATURE SPAN (°C) 1027 AI01
Kelvin Connections Figure 1. Maximum Allowable Reference Drift
Although the LT1027 does not have true force-sense capability, proper hook-up can improve line loss and
Trimming Output Voltage
ground loop problems significantly. Since the ground pin The LT1027 has an adjustment pin for trimming output of the LT1027 carries only 2mA, it can be used as a low- voltage. The impedance of the VADJ pin is about 20kΩ with side sense line, greatly reducing ground loop problems on an open-circuit voltage of 2.5V. A ±30mV guaranteed trim the low side of the reference. The VOUT pin should be close range is achievable by tying the VADJ pin to the wiper of a to the load or connected via a heavy trace as the resistance 10k potentiometer connecting between the output and of this trace directly affects load regulation. It is important ground. Trimming output voltage does not affect the TC of to remember that a 1.22mV drop due to trace resistance is the device. equivalent to a 1LSB error in a 5VFS, 12-bit system. The circuits in Figures 2 and 3 illustrate proper hook-up to
Noise Reduction
minimize errors due to ground loops and line losses. The positive input of the internal scaling amplifier is Losses in the output lead can be further reduced by adding brought out as the Noise Reduction (NR) pin. Connecting a PNP boost transistor if load current is 5mA or higher. R2 a 1µF Mylar capacitor between this pin and ground will can be added to further reduce current in the output sense reduce the wideband noise of the LT1027 from 2.0µV load. RMS sn1027 1027fcs 5
O U U W U APPLICATI S I FOR ATIO Effect of Reference Drift on System Accuracy
to approximately 1.2µVRMS in a 10Hz to 1kHz bandwidth. Transient response is not affected by this capacitor. Start- A large portion of the temperature drift error budget in up settling time will increase to several milliseconds due many systems is the system reference voltage. Figure 1 to the 7kΩ impedance looking into the NR pin. The indicates the maximum temperature coefficient allowable capacitor must be a low leakage type. Electrolytics are not if the reference is to contribute no more than 0.5LSB error suitable for this application. Just 100nA leakage current to the overall system performance. The example shown is will result in a 150ppm error in output voltage. This pin is a 12-bit system designed to operate over a temperature the most sensitive pin on the device. For maximum protec- range from 25°C to 65°C. Assuming the system calibra- tion a guard ring is recommended. The ring should be tion is performed at 25°C, the temperature span is 40°C. driven from a resistive divider from V It can be seen from the graph that the temperature coeffi- OUT set to 4.4V (the open-circuit voltage on the NR pin). cient of the reference must be no worse than 3ppm/°C if it is to contribute less than 0.5LSB error. For this reason,
Transient Response
the LT1027 has been optimized for low drift. The LT1027 has been optimized for transient response. 100 Settling time is under 2µs when an AC-coupled 10mA load 8-BIT transient is applied to the output. The LT1027 achieves °C) fast settling by using a class B NPN/PNP output stage. When sinking current, the device may oscillate with ca- 10-BIT 10 pacitive loads greater than 100pF. The LT1027 is stable with all capacitive loads when at no DC load or when 12-BIT sourcing current, although for best settling time either no 0.5LSB ERROR (ppm/ 14-BIT output bypass capactor or a 4.7µF tantalum unit is recom- mended. An 0.1µF ceramic output capacitor will maximize MAXIMUM TEMPERATURE COEFFICIENT FOR 1.0 0 10 20 40 50 60 70 80 90 100 output ringing and is not recommended. 30 TEMPERATURE SPAN (°C) 1027 AI01
Kelvin Connections Figure 1. Maximum Allowable Reference Drift
Although the LT1027 does not have true force-sense capability, proper hook-up can improve line loss and
Trimming Output Voltage
ground loop problems significantly. Since the ground pin The LT1027 has an adjustment pin for trimming output of the LT1027 carries only 2mA, it can be used as a low- voltage. The impedance of the VADJ pin is about 20kΩ with side sense line, greatly reducing ground loop problems on an open-circuit voltage of 2.5V. A ±30mV guaranteed trim the low side of the reference. The VOUT pin should be close range is achievable by tying the VADJ pin to the wiper of a to the load or connected via a heavy trace as the resistance 10k potentiometer connecting between the output and of this trace directly affects load regulation. It is important ground. Trimming output voltage does not affect the TC of to remember that a 1.22mV drop due to trace resistance is the device. equivalent to a 1LSB error in a 5VFS, 12-bit system. The circuits in Figures 2 and 3 illustrate proper hook-up to
Noise Reduction
minimize errors due to ground loops and line losses. The positive input of the internal scaling amplifier is Losses in the output lead can be further reduced by adding brought out as the Noise Reduction (NR) pin. Connecting a PNP boost transistor if load current is 5mA or higher. R2 a 1µF Mylar capacitor between this pin and ground will can be added to further reduce current in the output sense reduce the wideband noise of the LT1027 from 2.0µV load. RMS sn1027 1027fcs 5
