Datasheet ADE7754 (Analog Devices) - 4

ADE7754 TIMING CHARACTERISTICS1, 2 (AVDD = DVDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz XTAL, TMIN to TMAX = –40 C to +85 C, unless otherwise noted.) Parameter Spec Unit Test Conditions/Comments
Write Timing t1 50 ns (min) CS Falling Edge to First SCLK Falling Edge t2 50 ns (min) SCLK Logic High Pulsewidth t3 50 ns (min) SCLK Logic Low Pulsewidth t4 10 ns (min) Valid Data Setup Time before Falling Edge of SCLK t5 5 ns (min) Data Hold Time after SCLK Falling Edge t6 400 ns (min) Minimum Time between the End of Data Byte Transfers t7 50 ns (min) Minimum Time between Byte Transfers during a Serial Write t8 100 ns (min) CS Hold Time after SCLK Falling Edge Read Timing t 3 9 4 µs (min) Minimum Time between Read Command (i.e., a Write to Communication Register) and Data Read t10 50 ns (min) Minimum Time between Data Byte Transfers during a Multibyte Read t 4 11 30 ns (min) Data Access Time after SCLK Rising Edge following a Write to the Communications Register t 5 12 100 ns (max) Bus Relinquish Time after Falling Edge of SCLK 10 ns (min) t 5 13 100 ns (max) Bus Relinquish Time after Rising Edge of CS 10 ns (min) NOTES 1Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5 ns
200 A IOL
(10% to 90%) and timed from a voltage level of 1.6 V. 2See timing diagrams below and Serial Interface section of this data sheet.
TO
3Minimum time between read command and data read for all registers except
OUTPUT 2.1V
wavmode register, which is t
PIN CL
9 = 500 ns min. 4
50pF
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
1.6mA IOH
5Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF Figure 1. Load Circuit for Timing Specifications capacitor. The time quoted in the timing characteristics is the true bus relin- quish time of the part and is independent of the bus loading.
t8 CS t1 t2 t t 3 6 t t 7 7 SCLK t4 t5 DIN 1 0 A5 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
Figure 2. Serial Write Timing
CS t1 t9 t10 SCLK DIN 0 0 A5 A4 A3 A2 A1 A0 t t t 13 11 12 DB7 DOUT DB0 DB7 DB0 COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE
Figure 3. Serial Read Timing –4– REV. 0 Document Outline FEATURES GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics TERMINOLOGY Measurement Error Phase Error Between Channels Power Supply Rejection ADC Offset Error Gain Error Gain Error Match POWER SUPPLY MONITOR ANALOG INPUTS ANALOG-TO-DIGITAL CONVERSION Antialias Filter CURRENT CHANNEL ADC Current Channel ADC Gain Adjust Current Channel Sampling VOLTAGE CHANNEL ADC ZERO-CROSSING DETECTION Zero-Crossing Timeout PERIOD MEASUREMENT LINE VOLTAGE SAG DETECTION SAG Level Set PEAK DETECTION Peak Level Set TEMPERATURE MEASUREMENT PHASE COMPENSATION ROOT MEAN SQUARE MEASUREMENT Current RMS Calculation Current RMS Gain Adjust Current RMS Offset Compensation Voltage RMS Calculation Voltage RMS Gain Adjust Voltage RMS Offset Compensation ACTIVE POWER CALCULATION Power Offset Calibration Reverse Power Information TOTAL ACTIVE POWER CALCULATION ENERGY CALCULATION Integration Times Under Steady Load Energy to Frequency Conversion No Load Threshold Mode Selection of the Sum of the Three Active Energies LINE ENERGY ACCUMULATION REACTIVE POWER CALCULATION TOTAL REACTIVE POWER CALCULATION Reactive Energy Accumulation Selection APPARENT POWER CALCULATION Apparent Power Offset Calibration TOTAL APPARENT POWER CALCULATION APPARENT ENERGY CALCULATION Integration Times under Steady Load LINE APPARENT ENERGY ACCUMULATION ENERGIES SCALING CHECK SUM REGISTER SERIAL INTERFACE Serial Write Operation Serial Read Operation INTERRUPTS Using Interrupts with an MCU Interrupt Timing ACCESSING THE ADE7754 ON-CHIP REGISTERS Communications Register Operational Mode Register (0Ah) Gain Register (18h) CFNUM Register (25h) Measurement Mode Register (0Bh) Waveform Mode Register (0Ch) Watt Mode Register (0Dh) VA Mode Register (0Eh) Interrupt Enable Register (0Fh) Interrupt Status Register (10h)/Reset Interrupt Status Register (11h) OUTLINE DIMENSIONS