Datasheet LT1395, LT1396, LT1397 (Analog Devices) - 10

LT1395/LT1396/LT1397
APPLICATIONS INFORMATION Feedback Resistor Selection Slew Rate
The small-signal bandwidth of the LT1395/LT1396/LT1397 Unlike a traditional voltage feedback op amp, the slew rate is set by the external feedback resistors and the inter- of a current feedback amplifi er is not independent of the nal junction capacitors. As a result, the bandwidth is a amplifi er gain confi guration. In a current feedback ampli- function of the supply voltage, the value of the feedback fi er, both the input stage and the output stage have slew resistor, the closed-loop gain and the load resistor. The rate limitations. In the inverting mode, and for gains of 2 LT1395/LT1396/LT1397 have been optimized for ± 5V or more in the noninverting mode, the signal amplitude supply operation and have a –3dB bandwidth of 400MHz between the input pins is small and the overall slew rate at a gain of 1 and 350MHz at a gain of 2. Please refer to is that of the output stage. For gains less than 2 in the the resistor selection guide in the Typical AC Perfor- noninverting mode, the overall slew rate is limited by the mance table. input stage. The input slew rate of the LT1395/LT1396/LT1397 is ap-
Capacitance on the Inverting Input
proximately 600V/μs and is set by internal currents and Current feedback amplifi ers require resistive feedback from capacitances. The output slew rate is set by the value of the output to the inverting input for stable operation. Take the feedback resistor and internal capacitance. At a gain care to minimize the stray capacitance between the output of 2 with 255Ω feedback and gain resistors and ± 5V and the inverting input. Capacitance on the inverting input supplies, the output slew rate is typically 800V/μs. Larger to ground will cause peaking in the frequency response feedback resistors will reduce the slew rate as will lower (and overshoot in the transient response). supply voltages.
Capacitive Loads Enable/Disable
The LT1395/LT1396/LT1397 can drive many capacitive The LT1395CS6 has a unique high impedance, zero sup- loads directly when the proper value of feedback resistor ply current mode which is controlled by the EN pin. The is used. The required value for the feedback resistor will LT1395CS6 is designed to operate with CMOS logic; it increase as load capacitance increases and as closed- draws virtually zero current when the EN pin is high. To loop gain decreases. Alternatively, a small resistor (5Ω activate the amplifi er, its EN pin is normally pulled to a to 35Ω) can be put in series with the output to isolate the logic low. However, supply current will vary as the volt- capacitive load from the amplifi er output. This has the age between the V + supply and EN is varied. As seen advantage that the amplifi er bandwidth is only reduced in Figure 1, +IS does vary with (V+ – VEN), particularly when the capacitive load is present. The disadvantage is when the voltage difference is less than 3V. For normal that the gain is a function of the load resistance. See the 5.0 Typical Performance Characteristics curves. TA = 25°C 4.5 V+ = 5V 4.0
Power Supplies
V– = 0V 3.5 The LT1395/LT1396/LT1397 will operate from single or split 3.0 V– = –5V supplies from ± 2V (4V total) to ±6V (12V total). It is not (mA) 2.5 S necessary to use equal value split supplies, however the +I 2.0 offset voltage and inverting input bias current will change. 1.5 The offset voltage changes about 2.5mV per volt of supply 1.0 mismatch. The inverting bias current will typically change 0.5 about 10μA per volt of supply mismatch. 0 0 1 2 3 4 5 6 7 V+ – VEN (V) 1395/6/7 F01
Figure 1. + IS vs (V+ – VEN)
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