Datasheet ADP5080 (Analog Devices) - 10

ADP5080 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 4 5 6 7 8 9 VOUT6 VOUT6 VISW1 VISW2 PVINCP C+ PGND5 SW5 PVIN5 A SW6B SW6B VREG1 VREG2 VOLDO7 C– PGND5 SW5 PVIN5 B PGND6 PGND6 VBATT EN34 VILDO7 BSTCP VDR5 BST45 PVIN4 C SW6A SW6A VDR6 FB6 GND SYNC FB5 FB4 SW4 D PVIN6 PVIN6 BST16 SDA SCL GND CLKO VDR34 PGND4 E PVIN1 PVIN1 FB1 EN VDDIO FREQ FB3 PGND3 PGND3 F SW1A SW1B VDR12 FB2 GND FAULT GND SW3 SW3 G PGND1 PGND1 PGND2 SW2 SW2 PVIN2 BST23 PVIN3 PVIN3 H TOP VIEW
003
(BALL SIDE DOWN) Not to Scale
1639- 1 Figure 3. Pin Configuration
Table 8. Pin Function Descriptions Pin No. Mnemonic Description
1A VOUT6 Output Voltage for Channel 6. 2A VOUT6 Output Voltage for Channel 6. 3A VISW1 Input for an External Regulator Output. A 5.0 V to 5.5 V regulator connected to the VISW1 pin can take over from LDO1 to supply the internal circuit of the ADP5080 and the VREG1 load. If this pin is not used, connect it to GND. 4A VISW2 Input for an External Regulator Output. A 3.0 V to 3.3 V regulator connected to the VISW2 pin can take over from LDO2 to supply the internal circuit of the ADP5080 and the VREG2 load. If this pin is not used, connect it to GND. 5A PVINCP Input Power Supply for the Charge Pump. 6A C+ Flying Capacitor Terminal for the Charge Pump. 7A PGND5 Power Ground for Channel 5. 8A SW5 Switching Node for Channel 5. 9A PVIN5 Input Power Supply for Channel 5. 1B SW6B Secondary Side Boost Switching Node for Channel 6. 2B SW6B Secondary Side Boost Switching Node for Channel 6. 3B VREG1 Output Voltage for LDO1. 4B VREG2 Output Voltage for LDO2. 5B VOLDO7 Output Voltage for Channel 7. Leave this pin open if not used. 6B C− Flying Capacitor Terminal for the Charge Pump. 7B PGND5 Power Ground for Channel 5. 8B SW5 Switching Node for Channel 5. 9B PVIN5 Input Power Supply for Channel 5. 1C PGND6 Power Ground for Channel 6. 2C PGND6 Power Ground for Channel 6. 3C VBATT Power Supply Input for the Internal Circuits. Connect this pin to the battery. 4C EN34 Independent Enable Input for Channel 3 and Channel 4. If this pin is not used, connect it to GND. 5C VILDO7 Input Power Supply for Channel 7. If this pin is not used, connect it to VBATT. 6C BSTCP Output Voltage for Charge Pump. 7C VDR5 Low-Side FET Driver Power Supply for Channel 5. Connect this pin to VREG1. 8C BST45 High-Side FET Driver Power Supply for Channel 4 and Channel 5. Rev. A | Page 10 of 64 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Housekeeping Block Specifications DC-to-DC Converter Block Specifications Linear Regulator Block Specifications I2C Interface Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Application Circuit Theory of Operation UVLO and POR Undervoltage Lockout (UVLO) Power-On Reset (POR) Discharge Switch Keep-Alive LDO Linear Regulators LDO1 VISW1 Input Current Limit for LDO1 Discharge Switch for LDO1 LDO2 VISW2 Input Current Limit for LDO2 Discharge Switch for LDO2 DC-to-DC Converter Channels Channel 1, Channel 2, and Channel 3: Buck Regulators with Flex-Mode Architecture Selecting the Output Voltage, Channel 1 to Channel 3 Current-Limit Protection, Channel 1 to Channel 3 Discharge Switch, Channel 1 to Channel 3 Gate Scaling (Channel 1 Only) Dynamic Voltage Scaling (DVS) Function Channel 4 and Channel 5: Current Mode Buck Regulators Selecting the Output Voltage, Channel 4 and Channel 5 Current-Limit Protection, Channel 4 and Channel 5 Discharge Switch, Channel 4 and Channel 5 Channel 6: Buck or Buck Boost Regulator Buck Only Configuration Buck Boost Configuration Selecting the Output Voltage, Channel 6 Current-Limit Protection, Channel 6 Discharge Switch, Channel 6 Light Load and Other Modes of Operation for the DC-to-DC Converter Channels Slew Rate Adjustment Forced PWM (FPWM) Mode Auto DCM Auto PSM Selecting Light Load Switching Modes Switching Clock External Synchronization Mode Selecting the Internal Clock Frequency Selecting the External Resistor Phase Shifting CLKO Pin Soft Start Function Channel 7: High Voltage LDO Regulator Selecting the Output Voltage, Channel 7 Discharge Switch, Channel 7 Charge Pump Charge Pump Switching Frequency Capacitor Selection Protection Diode Using the Charge Pump as the Channel 7 Input Supply Enabling and Disabling the Output Channels Sequencer Mode Manual Mode EN Function EN34 Function Power-Good Function Fault Function Undervoltage Protection (UVP) UVP Detection Delay Channel 5 Standalone Undervoltage Detection Option Recovering from UVP Overvoltage Protection (OVP) OVP Detection Delay Recovering from OVP Applications Information Component Selection for the Buck and Buck Boost Regulators Setting the Output Voltage (Adjustable Mode Channels) Selecting the Inductor Selecting the Input Capacitor Selecting the Output Capacitor Component Selection for the LDO Regulators Selecting the Capacitors PCB Layout Recommendations Sensitive Signal Treatment Grounding External Component Placement and Signal Routing Thermal Considerations I2C Interface SDA and SCL Pins I2C Address Self-Clearing Register Bits I2C Interface Timing Diagrams Control Register Information Control Register Map CONTROL REGISTER DETAILS Register 1: DSCG (Discharge Switch Control), Address 0x01 Register 2: SFTTIM1234 (Soft Start Time for Channel 1, Channel 2, Channel 3, and Channel 4), Address 0x02 Register 3: SFTTIM567 (Soft Start Time for Channel 5, Channel 6, and Channel 7), Address 0x03 Register 4: EN_DLY12 (Enable Delay Time for Channel 1 and Channel 2), Address 0x04 Register 5: EN_DLY34 (Enable Delay Time for Channel 3 and Channel 4), Address 0x05 Register 6: EN_DLY56 (Enable Delay Time for Channel 5 and Channel 6), Address 0x06 Register 7: EN_DLY7 (Enable Delay Time for Channel 7), Address 0x07 Register 8: DIS_DLY12 (Disable Delay Time for Channel 1 and Channel 2), Address 0x08 Register 9: DIS_DLY34 (Disable Delay Time for Channel 3 and Channel 4), Address 0x09 Register 10: DIS_DLY56 (Disable Delay Time for Channel 5 and Channel 6), Address 0x0A Register 11: DIS_DLY7 (Disable Delay Time for Channel 7), Address 0x0B Register 12: VID1 (Output Voltage for Channel 1), Address 0x0C Register 13: VID23 (Output Voltage for Channel 2 and Channel 3), Address 0x0D Register 14: VID45 (Output Voltage for Channel 4 and Channel 5), Address 0x0E Register 15: VID6 (Output Voltage for Channel 6), Address 0x0F Register 16: VID7_LDO12 (Output Voltage for Channel 7, LDO1, and LDO2), Address 0x10 Register 17: DVS12 (DVS Control for Channel 1 and Channel 2), Address 0x11 Register 18: SEL_FREQ (Switching Frequency for Channel 1 to Channel 6), Address 0x12 Register 19: SEL_FREQ_CP (Charge Pump Frequency), Address 0x13 Register 20: SEL_PHASE (Switching Phase for Channel 1 to Channel 6), Address 0x14 Register 23: PROT_DLY (Undervoltage/Overvoltage Protection Delay Times), Address 0x17 Register 24: PWRG (Power-Good Status), Address 0x18 Register 25: MASK_PWRG (Power-Good Masked Channels), Address 0x19 Register 26: UVPST (Undervoltage Protection Status), Address 0x1A Register 27: OVPST (Overvoltage Protection Status), Address 0x1B Register 28: AUTO-PSM (Auto PSM or Forced PWM Mode for Channel 1 to Channel 6), Address 0x1C Register 29: SEQ_MODE (Sequencer Mode), Address 0x1D Register 30: ADJ_BST_VTH6 (Adjust Boost Kick-In Threshold and Regulation Mode for Channel 6), Address 0x1E Register 31: OPT_SR_ADJ (Slew Rate Adjustment for Channel 1 to Channel 6), Address 0x1F Register 32: DCM56_GSCAL1 (Auto DCM for Channel 5 and Channel 6, Gate Scaling for Channel 1), Address 0x20 Register 33: SEL_INP_LDO12 (Input Selection for LDO1 and LDO2), Address 0x21 Register 34: SEL_IND_UV5 (Independent UVP Control for Channel 5), Address 0x22 Register 35: OPTION_SEL (Channel 1 Output Voltage Reduction, Disable Delay Time Increase, EN34 Function), Address 0x23 Register 48: PCTRL (Channel Enable Control), Address 0x30 Factory Default Options Outline Dimensions Ordering Guide