Datasheet ADP5052 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator |
| Pages / Page | 36 / 10 — ADP5052. Data Sheet. Pin No. Mnemonic. Description |
| Revision | D |
| File Format / Size | PDF / 1.1 Mb |
| Document Language | English |
ADP5052. Data Sheet. Pin No. Mnemonic. Description
Model Line for this Datasheet
Text Version of Document
link to page 19 link to page 20 link to page 18 link to page 19
ADP5052 Data Sheet Pin No. Mnemonic Description
33, 34 SW1 Switching Node Output for Channel 1. 35, 36 PVIN1 Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass capacitor between this pin and ground. 37 EN1 Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold. 38 SS12 Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and Channel 2 (see the Soft Start section). This pin is also used to configure parallel operation of Channel 1 and Channel 2 (see the Parallel Operation section). 39 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground. 40 FB1 Feedback Sensing Input for Channel 1. 41 RT Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 1.4 MHz. For more information, see the Oscillator section. 42 VDD Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground. 43 SYNC/MODE Synchronization Input/Output (SYNC). To synchronize the switching frequency of the part to an external clock, connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. This pin can also be configured as a synchronization output by factory fuse. Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, the part operates in forced PWM (FPWM) mode. When this pin is logic low, the part operates in automatic PWM/PSM mode. 44 VREG Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground. 45 FB3 Feedback Sensing Input for Channel 3. 46 COMP3 Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground. 47 SS34 Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and Channel 4 (see the Soft Start section). 48 EN3 Enable Input for Channel 3. An external resistor divider can be used to set the turn-on threshold. EPAD Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane. Rev. D | Page 10 of 36 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN LDO REGULATOR APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
ADP5052 Data Sheet Pin No. Mnemonic Description
33, 34 SW1 Switching Node Output for Channel 1. 35, 36 PVIN1 Power Input for the Internal 5.1 V VREG Linear Regulator and the Channel 1 Buck Regulator. Connect a bypass capacitor between this pin and ground. 37 EN1 Enable Input for Channel 1. An external resistor divider can be used to set the turn-on threshold. 38 SS12 Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 1 and Channel 2 (see the Soft Start section). This pin is also used to configure parallel operation of Channel 1 and Channel 2 (see the Parallel Operation section). 39 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground. 40 FB1 Feedback Sensing Input for Channel 1. 41 RT Connect a resistor from RT to ground to program the switching frequency from 250 kHz to 1.4 MHz. For more information, see the Oscillator section. 42 VDD Output of the Internal 3.3 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground. 43 SYNC/MODE Synchronization Input/Output (SYNC). To synchronize the switching frequency of the part to an external clock, connect this pin to an external clock with a frequency from 250 kHz to 1.4 MHz. This pin can also be configured as a synchronization output by factory fuse. Forced PWM or Automatic PWM/PSM Selection Pin (MODE). When this pin is logic high, the part operates in forced PWM (FPWM) mode. When this pin is logic low, the part operates in automatic PWM/PSM mode. 44 VREG Output of the Internal 5.1 V Linear Regulator. Connect a 1 µF ceramic capacitor between this pin and ground. 45 FB3 Feedback Sensing Input for Channel 3. 46 COMP3 Error Amplifier Output for Channel 3. Connect an RC network from this pin to ground. 47 SS34 Connect a resistor divider from this pin to VREG and ground to configure the soft start time for Channel 3 and Channel 4 (see the Soft Start section). 48 EN3 Enable Input for Channel 3. An external resistor divider can be used to set the turn-on threshold. EPAD Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane. Rev. D | Page 10 of 36 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION THERMAL SHUTDOWN LDO REGULATOR APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
