Datasheet ADP5050 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator |
| Pages / Page | 55 / 3 — Data Sheet. ADP5050. REVISION HISTORY 10/2016—Rev. B to Rev. C. … |
| Revision | C |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
Data Sheet. ADP5050. REVISION HISTORY 10/2016—Rev. B to Rev. C. 9/2015—Rev. A to Rev. B. 3/2014—Rev. 0 to Rev. A
Model Line for this Datasheet
Text Version of Document
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Data Sheet ADP5050
Register 4: VID4 (VID Setting for Channel 4), Address 0x04 Register 11: PWRGD_MASK (Channel Mask Configuration ... 43 for PWRGD Pin), Address 0x0B ... 50 Register 5: DVS_CFG (DVS Configuration for Channel 1 and Register 12: LCH_STATUS (Latch-Off Status Readback), Channel 4), Address 0x05 .. 44 Address 0x0C ... 51 Register 6: OPT_CFG (FPWM/PSM Mode and Output Register 13: STATUS_RD (Status Readback), Address 0x0D Discharge Function Configuration), Address 0x06 ... 45 ... 51 Register 7: LCH_CFG (Short-Circuit Latch-Off and Register 14: INT_STATUS (Interrupt Status Readback), Overvoltage Latch-Off Configuration), Address 0x07 .. 46 Address 0x0E ... 52 Register 8: SW_CFG (Switching Frequency and Phase Shift Register 15: INT_MASK (Interrupt Mask Configuration), Configuration), Address 0x08 ... 47 Address 0x0F ... 53 Register 9: TH_CFG (Temperature Warning and Low VIN Register 17: DEFAULT_SET (Default Reset), Address 0x11 .53 Warning Threshold Configuration), Address 0x09 .. 48 Factory Default Options ... 54 Register 10: HICCUP_CFG (Hiccup Configuration), Outline Dimensions .. 55 Address 0x0A ... 49 Ordering Guide ... 55
REVISION HISTORY 10/2016—Rev. B to Rev. C
Deleted Factory Programmable Options Section and Table 52 to Table 65; Renumbered Sequential y .. 54 Changes to Factory Default Options Section .. 54 Updated Outline Dimensions .. 55
9/2015—Rev. A to Rev. B
Changes to Figure 1 and Table 1 ... 1
3/2014—Rev. 0 to Rev. A
Changed Pin 13 from nINT to INT .. Throughout Added Table 1; Renumbered Sequential y ... 1 Changes to Figure 8... 13 Changes to Figure 12 .. 14 Changes to Table 14 .. 30 Updated Outline Dimensions (Exposed Paddle Changed for JEDEC Compliance) ... 57
5/2013—Revision 0: Initial Version
Rev. C | Page 3 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet ADP5050
Register 4: VID4 (VID Setting for Channel 4), Address 0x04 Register 11: PWRGD_MASK (Channel Mask Configuration ... 43 for PWRGD Pin), Address 0x0B ... 50 Register 5: DVS_CFG (DVS Configuration for Channel 1 and Register 12: LCH_STATUS (Latch-Off Status Readback), Channel 4), Address 0x05 .. 44 Address 0x0C ... 51 Register 6: OPT_CFG (FPWM/PSM Mode and Output Register 13: STATUS_RD (Status Readback), Address 0x0D Discharge Function Configuration), Address 0x06 ... 45 ... 51 Register 7: LCH_CFG (Short-Circuit Latch-Off and Register 14: INT_STATUS (Interrupt Status Readback), Overvoltage Latch-Off Configuration), Address 0x07 .. 46 Address 0x0E ... 52 Register 8: SW_CFG (Switching Frequency and Phase Shift Register 15: INT_MASK (Interrupt Mask Configuration), Configuration), Address 0x08 ... 47 Address 0x0F ... 53 Register 9: TH_CFG (Temperature Warning and Low VIN Register 17: DEFAULT_SET (Default Reset), Address 0x11 .53 Warning Threshold Configuration), Address 0x09 .. 48 Factory Default Options ... 54 Register 10: HICCUP_CFG (Hiccup Configuration), Outline Dimensions .. 55 Address 0x0A ... 49 Ordering Guide ... 55
REVISION HISTORY 10/2016—Rev. B to Rev. C
Deleted Factory Programmable Options Section and Table 52 to Table 65; Renumbered Sequential y .. 54 Changes to Factory Default Options Section .. 54 Updated Outline Dimensions .. 55
9/2015—Rev. A to Rev. B
Changes to Figure 1 and Table 1 ... 1
3/2014—Rev. 0 to Rev. A
Changed Pin 13 from nINT to INT .. Throughout Added Table 1; Renumbered Sequential y ... 1 Changes to Figure 8... 13 Changes to Figure 12 .. 14 Changes to Table 14 .. 30 Updated Outline Dimensions (Exposed Paddle Changed for JEDEC Compliance) ... 57
5/2013—Revision 0: Initial Version
Rev. C | Page 3 of 55 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS LDO REGULATOR SPECIFICATIONS I2C INTERFACE TIMING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode Forced PWM and Automatic PWM/PSM Modes ADJUSTABLE AND FIXED OUTPUT VOLTAGES DYNAMIC VOLTAGE SCALING (DVS) INTERNAL REGULATORS (VREG AND VDD) SEPARATE SUPPLY APPLICATIONS LOW-SIDE DEVICE SELECTION BOOTSTRAP CIRCUITRY ACTIVE OUTPUT DISCHARGE SWITCH PRECISION ENABLING OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT SOFT START PARALLEL OPERATION STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLDBACK Pulse Skip Mode Under Maximum Duty Cycle HICCUP PROTECTION LATCH-OFF PROTECTION Short-Circuit Latch-Off Mode Overvoltage Latch-Off Mode UNDERVOLTAGE LOCKOUT (UVLO) POWER-GOOD FUNCTION INTERRUPT FUNCTION THERMAL SHUTDOWN OVERHEAT DETECTION LOW INPUT VOLTAGE DETECTION LDO REGULATOR I2C INTERFACE SDA AND SCL PINS I2C ADDRESSES SELF-CLEAR REGISTER BITS I2C INTERFACE TIMING DIAGRAMS APPLICATIONS INFORMATION ADIsimPower DESIGN TOOL PROGRAMMING THE ADJUSTABLE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION LOW-SIDE POWER DEVICE SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown LDO Regulator Power Dissipation JUNCTION TEMPERATURE DESIGN EXAMPLE SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CURRENT LIMIT SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR SELECTING THE LOW-SIDE MOSFET DESIGNING THE COMPENSATION NETWORK SELECTING THE SOFT START TIME SELECTING THE INPUT CAPACITOR RECOMMENDED EXTERNAL COMPONENTS CIRCUIT BOARD LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS REGISTER MAP DETAILED REGISTER DESCRIPTIONS REGISTER 1: PCTRL (CHANNEL ENABLE CONTROL), ADDRESS 0x01 REGISTER 2: VID1 (VID SETTING FOR CHANNEL 1), ADDRESS 0x02 REGISTER 3: VID23 (VID SETTING FOR CHANNEL 2 AND CHANNEL 3), ADDRESS 0x03 REGISTER 4: VID4 (VID SETTING FOR CHANNEL 4), ADDRESS 0x04 REGISTER 5: DVS_CFG (DVS CONFIGURATION FOR CHANNEL 1 AND CHANNEL 4), ADDRESS 0x05 REGISTER 6: OPT_CFG (FPWM/PSM MODE AND OUTPUT DISCHARGE FUNCTION CONFIGURATION), ADDRESS 0x06 REGISTER 7: LCH_CFG (SHORT-CIRCUIT LATCH-OFF AND OVERVOLTAGE LATCH-OFF CONFIGURATION), ADDRESS 0x07 REGISTER 8: SW_CFG (SWITCHING FREQUENCY AND PHASE SHIFT CONFIGURATION), ADDRESS 0x08 REGISTER 9: TH_CFG (TEMPERATURE WARNING AND LOW VIN WARNING THRESHOLD CONFIGURATION), ADDRESS 0x09 REGISTER 10: HICCUP_CFG (HICCUP CONFIGURATION), ADDRESS 0x0A REGISTER 11: PWRGD_MASK (CHANNEL MASK CONFIGURATION FOR PWRGD PIN), ADDRESS 0x0B REGISTER 12: LCH_STATUS (LATCH-OFF STATUS READBACK), ADDRESS 0x0C REGISTER 13: STATUS_RD (STATUS READBACK), ADDRESS 0x0D REGISTER 14: INT_STATUS (INTERRUPT STATUS READBACK), ADDRESS 0x0E REGISTER 15: INT_MASK (INTERRUPT MASK CONFIGURATION), ADDRESS 0x0F REGISTER 17: DEFAULT_SET (DEFAULT RESET), ADDRESS 0x11 FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
