Datasheet LTC3407A (Analog Devices) - 10

LTC3407A
APPLICATIONS INFORMATION
Since the ESR of a ceramic capacitor is so low, the input
Power-On Reset
and output capacitor must instead fulfi ll a charge storage The POR pin is an open-drain output which pulls low when requirement. During a load step, the output capacitor must either regulator is out of regulation. When both output instantaneously supply the current to support the load voltages are within ±8.5% of regulation, a timer is started until the feedback loop raises the switch current enough to support the load. The time required for the feedback which releases POR after 216 clock cycles (about 44ms loop to respond is dependent on the compensation and in pulse skipping mode). This delay can be signifi cantly the output capacitor size. Typically, 3-4 cycles are required longer in Burst Mode operation with low load currents, to respond to a load step, but only in the fi rst cycle does since the clock cycles only occur during a burst and there the output drop linearly. The output droop, V could be milliseconds of time between bursts. This can DROOP, is usually about 3 times the linear drop of the fi rst cycle. be bypassed by tying the POR output to the MODE/SYNC Thus, a good place to start is with the output capacitor input, to force pulse skipping mode during a reset. In size of approximately: addition, if the output voltage faults during Burst Mode sleep, POR could have a slight delay for an undervoltage COUT ≈3 ΔIOUT output condition and may not respond to an overvoltage f O • VDROOP output. This can be avoided by using pulse skipping mode More capacitance may be required depending on the duty instead. When either channel is shut down, the POR output cycle and load step requirements. is pulled low, since one or both of the channels are not in regulation. In most applications, the input capacitor is merely required to supply high frequency bypassing, since the impedance
Mode Selection & Frequency Synchronization
to the supply is very low. A 10μF ceramic capacitor is usually enough for these conditions. The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. Connect-
Setting the Output Voltage
ing this pin to VIN enables Burst Mode operation, which provides the best low current effi ciency at the cost of a The LTC3407A develops a 0.6V reference voltage between higher output voltage ripple. When this pin is connected the feedback pin, VFB, and ground as shown in Figure 1. to ground, pulse skipping operation is selected which The output voltage is set by a resistive divider according provides the lowest output ripple, at the cost of low cur- to the following formula: rent effi ciency. VOUT = 0.6V 1+ R2 The LTC3407A can also be synchronized to another R1 LTC3407A by the MODE/SYNC pin. During synchroniza- tion, the mode is set to pulse skipping and the top switch Keeping the current small (<5μA) in these resistors maxi- turn-on is synchronized to the rising edge of the external mizes effi ciency, but making them too small may allow stray capacitance to cause noise problems and reduce the clock. phase margin of the error amp loop.
Checking Transient Response
To improve the frequency response, a feed-forward capaci- The regulator loop response can be checked by look- tor CF may also be used. Great care should be taken to ing at the load transient response. Switching regulators route the VFB line away from noise sources, such as the inductor or the SW line. take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. 3407afa 10