Datasheet LT3510 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Monolithic Dual Tracking 2A Step-Down Switching Regulator |
| Pages / Page | 30 / 9 — PIN FUNCTIONS. BST1/BST2 (Pins 20, 11):. Exposed Pad (Pin 21):. only |
| File Format / Size | PDF / 358 Kb |
| Document Language | English |
PIN FUNCTIONS. BST1/BST2 (Pins 20, 11):. Exposed Pad (Pin 21):. only
Model Line for this Datasheet
Text Version of Document
LT3510
PIN FUNCTIONS
the clock signal is detected, with switch 1 in phase with
BST1/BST2 (Pins 20, 11):
The BST pin provides a higher the synchronization signal. Each rising clock edge initiates than VIN base drive to the power NPN to ensure a low an oscillator ramp reset. A gain control loop servos the switch drop. A comparator to VIN imposes a minimum oscillator charging current to maintain a constant oscillator off time on the SW pin if the BST pin voltage drops too amplitude. Hence, the slope compensation and channel low. Forcing a SW off time allows the boost capacitor to phase relationship remain unchanged. If the clock signal recharge. is removed, the oscillator reverts to resistor mode and
Exposed Pad (Pin 21):
GND. The Exposed Pad GND pin is reapplies the 0.975V bias to the RT/SYNC pin after the the
only
ground connection for the device. The Exposed synchronization detection circuitry times out. The clock Pad should be soldered to a large copper area to reduce source impedance should be set such that the current out thermal resistance. The GND pin is common to both chan- of the RT/SYNC pin in resistor mode generates a frequency nels and also serves as small-signal ground. For ideal roughly equivalent to the synchronization frequency. operation all small-signal ground paths should connect to the GND pin at a single point, avoiding any high current ground returns. 3510fe 9 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
PIN FUNCTIONS
the clock signal is detected, with switch 1 in phase with
BST1/BST2 (Pins 20, 11):
The BST pin provides a higher the synchronization signal. Each rising clock edge initiates than VIN base drive to the power NPN to ensure a low an oscillator ramp reset. A gain control loop servos the switch drop. A comparator to VIN imposes a minimum oscillator charging current to maintain a constant oscillator off time on the SW pin if the BST pin voltage drops too amplitude. Hence, the slope compensation and channel low. Forcing a SW off time allows the boost capacitor to phase relationship remain unchanged. If the clock signal recharge. is removed, the oscillator reverts to resistor mode and
Exposed Pad (Pin 21):
GND. The Exposed Pad GND pin is reapplies the 0.975V bias to the RT/SYNC pin after the the
only
ground connection for the device. The Exposed synchronization detection circuitry times out. The clock Pad should be soldered to a large copper area to reduce source impedance should be set such that the current out thermal resistance. The GND pin is common to both chan- of the RT/SYNC pin in resistor mode generates a frequency nels and also serves as small-signal ground. For ideal roughly equivalent to the synchronization frequency. operation all small-signal ground paths should connect to the GND pin at a single point, avoiding any high current ground returns. 3510fe 9 Document Outline FEATURES DESCRIPTION APPLICATIONS TYPICAL APPLICATION ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION ORDER INFORMATION ELECTRICAL CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS PIN FUNCTIONS BLOCK DIAGRAM APPLICATIONS INFORMATION TYPICAL APPLICATIONS PACKAGE DESCRIPTION REVISION HISTORY RELATED PARTS
