Datasheet LTC3407-4 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual Synchronous, 800mA, 2.25MHz Step-Down DC/DC Regulator |
| Pages / Page | 16 / 10 — APPLICATIONS INFORMATION. Checking Transient Response. Power-On Reset. … |
| File Format / Size | PDF / 275 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Checking Transient Response. Power-On Reset. Mode Selection & Frequency Synchronization
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Text Version of Document
LTC3407-4
APPLICATIONS INFORMATION
R2
Checking Transient Response
VOUT =0.6V 1 + R1 The regulator loop response can be checked by look- ing at the load transient response. Switching regulators Keeping the current small (<5μA) in these resistors maxi- take several cycles to respond to a step in load current. mizes effi ciency, but making them too small may allow When a load step occurs, VOUT immediately shifts by an stray capacitance to cause noise problems and reduce the amount equal to ΔILOAD • ESR, where ESR is the effective phase margin of the error amp loop. series resistance of COUT. ΔILOAD also begins to charge To improve the frequency response, a feed-forward capaci- or discharge COUT, generating a feedback error signal tor C used by the regulator to return V F may also be used. Great care should be taken to OUT to its steady-state route the V value. During this recovery time, V FB line away from noise sources, such as the OUT can be monitored inductor or the SW line. for overshoot or ringing that would indicate a stability problem.
Power-On Reset
The initial output voltage step may not be within the The POR pin is an open-drain output which pulls low bandwidth of the feedback loop, so the standard second- when either regulator is out of regulation. When both order overshoot/DC ratio cannot be used to determine output voltages are within ±8.5% of regulation, a timer is phase margin. In addition, a feed-forward capacitor, CF, started which releases POR after 216 clock cycles (about can be added to improve the high frequency response, as 29ms). This delay can be signifi cantly longer in Burst Mode shown in Figure 2. Capacitor CF provides phase lead by operation with low load currents, since the clock cycles creating a high frequency zero with R2, which improves only occur during a burst and there could be milliseconds the phase margin. of time between bursts. This can be bypassed by tying the POR output to the MODE/SYNC input, to force pulse-skip- The output voltage settling behavior is related to the stability ping mode during a reset. In addition, if the output voltage of the closed-loop system and will demonstrate the actual faults during Burst Mode sleep, POR could have a slight overall supply performance. For a detailed explanation of delay for an undervoltage output condition and may not optimizing the compensation components, including a re- respond to an overvoltage output. This can be avoided by view of control loop theory, refer to Application Note 76. using pulse-skipping mode instead. When either channel In some applications, a more severe transient can be caused is shut down, the POR output is pulled low, since one or by switching in loads with large (>1μF) input capacitors. both of the channels are not in regulation. The discharged input capacitors are effectively put in paral- lel with C
Mode Selection & Frequency Synchronization
OUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the The MODE/SYNC pin is a multipurpose pin which provides switch connecting the load has low resistance and is driven mode selection and frequency synchronization. Connect- quickly. The solution is to limit the turn-on speed of the ing this pin to VIN enables Burst Mode operation, which load switch driver. A Hot Swap™ controller is designed provides the best low current effi ciency at the cost of a specifi cally for this purpose and usually incorporates cur- higher output voltage ripple. Connecting this pin to ground rent limiting, short-circuit protection, and soft-starting. selects pulse-skipping mode, which provides the lowest output ripple, at the cost of low current effi ciency.
Effi ciency Considerations
The LTC3407-4 can also be synchronized to an external The percent effi ciency of a switching regulator is equal to 2.25MHz clock signal (such as the SW pin on another the output power divided by the input power times 100%. LTC3407-4) by the MODE/SYNC pin. During synchro- It is often useful to analyze individual losses to determine nization, the mode is set to pulse-skipping and the top what is limiting the effi ciency and which change would switch turn-on is synchronized to the rising edge of the Hot Swap is a trademark of Linear Technology Corporation. external clock. 34074fa 10
APPLICATIONS INFORMATION
R2
Checking Transient Response
VOUT =0.6V 1 + R1 The regulator loop response can be checked by look- ing at the load transient response. Switching regulators Keeping the current small (<5μA) in these resistors maxi- take several cycles to respond to a step in load current. mizes effi ciency, but making them too small may allow When a load step occurs, VOUT immediately shifts by an stray capacitance to cause noise problems and reduce the amount equal to ΔILOAD • ESR, where ESR is the effective phase margin of the error amp loop. series resistance of COUT. ΔILOAD also begins to charge To improve the frequency response, a feed-forward capaci- or discharge COUT, generating a feedback error signal tor C used by the regulator to return V F may also be used. Great care should be taken to OUT to its steady-state route the V value. During this recovery time, V FB line away from noise sources, such as the OUT can be monitored inductor or the SW line. for overshoot or ringing that would indicate a stability problem.
Power-On Reset
The initial output voltage step may not be within the The POR pin is an open-drain output which pulls low bandwidth of the feedback loop, so the standard second- when either regulator is out of regulation. When both order overshoot/DC ratio cannot be used to determine output voltages are within ±8.5% of regulation, a timer is phase margin. In addition, a feed-forward capacitor, CF, started which releases POR after 216 clock cycles (about can be added to improve the high frequency response, as 29ms). This delay can be signifi cantly longer in Burst Mode shown in Figure 2. Capacitor CF provides phase lead by operation with low load currents, since the clock cycles creating a high frequency zero with R2, which improves only occur during a burst and there could be milliseconds the phase margin. of time between bursts. This can be bypassed by tying the POR output to the MODE/SYNC input, to force pulse-skip- The output voltage settling behavior is related to the stability ping mode during a reset. In addition, if the output voltage of the closed-loop system and will demonstrate the actual faults during Burst Mode sleep, POR could have a slight overall supply performance. For a detailed explanation of delay for an undervoltage output condition and may not optimizing the compensation components, including a re- respond to an overvoltage output. This can be avoided by view of control loop theory, refer to Application Note 76. using pulse-skipping mode instead. When either channel In some applications, a more severe transient can be caused is shut down, the POR output is pulled low, since one or by switching in loads with large (>1μF) input capacitors. both of the channels are not in regulation. The discharged input capacitors are effectively put in paral- lel with C
Mode Selection & Frequency Synchronization
OUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem, if the The MODE/SYNC pin is a multipurpose pin which provides switch connecting the load has low resistance and is driven mode selection and frequency synchronization. Connect- quickly. The solution is to limit the turn-on speed of the ing this pin to VIN enables Burst Mode operation, which load switch driver. A Hot Swap™ controller is designed provides the best low current effi ciency at the cost of a specifi cally for this purpose and usually incorporates cur- higher output voltage ripple. Connecting this pin to ground rent limiting, short-circuit protection, and soft-starting. selects pulse-skipping mode, which provides the lowest output ripple, at the cost of low current effi ciency.
Effi ciency Considerations
The LTC3407-4 can also be synchronized to an external The percent effi ciency of a switching regulator is equal to 2.25MHz clock signal (such as the SW pin on another the output power divided by the input power times 100%. LTC3407-4) by the MODE/SYNC pin. During synchro- It is often useful to analyze individual losses to determine nization, the mode is set to pulse-skipping and the top what is limiting the effi ciency and which change would switch turn-on is synchronized to the rising edge of the Hot Swap is a trademark of Linear Technology Corporation. external clock. 34074fa 10
