Datasheet LT1940, LT1940L (Analog Devices) - 7

LT1940/LT1940L
W BLOCK DIAGRA
duty cycle of the power switch, the feedback loop controls Each switcher contains an independent oscillator. This the peak current in the switch during each cycle. This slave oscillator is normally synchronized to the master current mode control improves loop dynamics and pro- oscillator. However, during start-up, short-circuit or over- vides cycle-by-cycle current limit. load conditions, the FB pin voltage will be near zero and an internal comparator gates the master oscillator clock The Block Diagram shows only one of the two switching signal. This allows the slave oscillator to run the regulator regulators. A pulse from the slave oscillator sets the RS at a lower frequency. This frequency foldback behavior flip-flop and turns on the internal NPN bipolar power helps to limit switch current and power dissipation under switch. Current in the switch and the external inductor fault conditions. begins to increase. When this current exceeds a level determined by the voltage at V The switch driver operates from either the input or from C, current comparator C1 resets the flip-flop, turning off the switch. The current in the BOOST pin. An external capacitor and diode are used the inductor flows through the external Schottky diode, to generate a voltage at the BOOST pin that is higher than and begins to decrease. The cycle begins again at the next the input supply. This allows the driver to fully saturate the pulse from the oscillator. In this way the voltage on the V internal bipolar NPN power switch for efficient operation. C pin controls the current through the inductor to the output. A power good comparator trips when the FB pin is at 90% The internal error amplifier regulates the output voltage by of its regulated value. The PG output is an open collector continually adjusting the VC pin voltage. transistor that is off when the output is in regulation, The threshold for switching on the V allowing an external resistor to pull the PG pin high. Power C pin is 0.75V, and an active clamp of 1.8V limits the output current. The V good is valid when the LT1940 is enabled (either RUN/SS C pin is also clamped to the RUN/SS pin voltage. As the internal pin is high) and VIN is greater than ~2.4V. current source charges the external soft-start capacitor, the current limit increases slowly.
U U W U APPLICATIO S I FOR ATIO FB Resistor Network
where VD is the forward voltage drop of the catch diode (~0.4V) and V The output voltage is programmed with a resistor divider SW is the voltage drop of the internal switch (~0.3V at maximum load). This leads to a minimum input between the output and the FB pin. Choose the 1% voltage of: resistors according to: V R1 = R2(V INMIN = (VOUT + VD)/DCMAX - VD + VSW OUT/1.25 – 1) with DC R2 should be 10.0kΩ or less to avoid bias current errors. MAX = 0.78. Reference designators refer to the Block Diagram in A more detailed analysis includes inductor loss and the Figure␣ 2. dependence of the diode and switch drop on operating current. A common application where the maximum duty
Input Voltage Range
cycle limits the input voltage range is the conversion of The minimum input voltage is determined by either the 5V to 3.3V. The maximum load current that the LT1940 LT1940’s minimum operating voltage of ~3.5V, or by its can deliver at 3.3V depends on the accuracy of the 5V maximum duty cycle. The duty cycle is the fraction of time input supply. With a low loss inductor (DCR less than that the internal switch is on and is determined by the input 80mΩ), the LT1940 can deliver 1A for VIN > 4.7V and and output voltages: 1.4A for VIN > 4.85V. DC = (VOUT + VD)/(VIN – VSW + VD) 1940fa 7