Datasheet LTC1707 (Analog Devices) - 10

LTC1707
U U W U APPLICATIO S I FOR ATIO
D1 in Figure 5 reduces the start delay but allows CSS to both top and bottom MOSFET RDS(ON) and the duty ramp up slowly providing the soft-start function. This cycle (DC) as follows: diode can be deleted if soft-start is not needed. RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)
Efficiency Considerations
The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteris- The efficiency of a switching regulator is equal to the tics curves. Thus, to obtain I2R losses, simply add R output power divided by the input power times 100%. It is SW to R often useful to analyze individual losses to determine what L and multiply by the square of the average output current. is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Other losses including CIN and COUT ESR dissipative losses, MOSFET switching losses and inductor core and copper Efficiency = 100% – (L1 + L2 + L3 + ...) losses generally account for less than 2% total additional where L1, L2, etc. are the individual losses as a percentage loss. of input power. 1 V Although all dissipative elements in the circuit produce OUT = 1.5V VOUT = 3.3V losses, two main sources usually account for most of the VOUT = 5V losses in LTC1707 circuits: VIN quiescent current and I2R 0.1 losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load POWER LOST (W) 0.01 currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 6. VIN = 6V 0.001 1 10 100 1000 1. The VIN quiescent current is due to two components: the LOAD CURRENT (mA) DC bias current as given in the electrical characteristics 1707 F06 and the internal main switch and synchronous switch
Figure 6. Power Lost vs Load Current
gate charge currents. The gate charge current results from switching the gate capacitance of the internal power
Checking Transient Response
MOSFET switches. Each time the gate is switched from The regulator loop response can be checked by looking at high to low or from low to high, a packet of charge dQ the load transient response. Switching regulators take moves from VIN to ground. The resulting dQ/dt is the several cycles to respond to a step in load current. When current out of VIN that is typically larger than the DC bias a load step occurs, V current. In continuous mode, I OUT immediately shifts by an amount GATECHG = f(QT + QB) where equal to (∆I Q LOAD • ESR), where ESR is the effective series T and QB are the gate charges of the internal top and resistance of C bottom switches. Both the DC bias and gate charge losses OUT. ∆ILOAD also begins to charge or dis- charge C are proportional to V OUT, which generates a feedback error signal. The IN and thus their effects will be more regulator loop then acts to return V pronounced at higher supply voltages. OUT to its steady-state value. During this recovery time, VOUT can be monitored 2. I2R losses are calculated from the resistances of the for overshoot or ringing that would indicate a stability internal switches RSW and external inductor RL. In problem. The internal compensation provides adequate continuous mode the average output current flowing compensation for most applications. But if additional through inductor L is “chopped” between the main compensation is required, the ITH pin can be used for switch and the synchronous switch. Thus, the series external compensation as shown in Figure 7 (the 47pF resistance looking into SW pin from L is a function of capacitor, CC2, is typically needed for noise decoupling). 10