Datasheet ADP1850 (Analog Devices) - 4

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ADP1850 Data Sheet Parameter Symbol Conditions Min Typ Max Unit
GATE DRIVERS DHx Rise Time C = 3 nF, V − V = 5 V 16 ns DH BST SW DHx Fall Time C = 3 nF, V − V = 5 V 14 ns DH BST SW DLx Rise Time C = 3 nF 16 ns DL DLx Fall Time C = 3 nF 14 ns DL DHx to DLx Dead Time External 3 nF is connected to DHx and DLx 25 ns DHx or DLx Driver R , Sourcing R Sourcing 2 A with a 100 ns pulse 2 Ω ON ON_SOURCE Current1 Sourcing 1 A with a 100 ns pulse, V = 3 V 2.3 Ω IN DHx or DLx Driver R , Tempco TC V = 3 V or 12 V 0.3 %/oC ON RON IN DHx or DLx Driver R , Sinking R Sinking 2 A with a 100 ns pulse 1.5 Ω ON ON_SINK Current1 Sinking 1 A with a 100 ns pulse, V = 3 V 2 Ω IN DHx Maximum Duty Cycle f = 300 kHz 90 % SW DHx Maximum Duty Cycle f = 1500 kHz 50 % SW Minimum DHx On Time f = 200 kHz to 1500 kHz 135 ns SW Minimum DHx Off Time f = 200 kHz to 1500 kHz 335 ns SW Minimum DLx On Time f = 200 kHz to 1500 kHz 285 ns SW COMPx VOLTAGE RANGE COMPx Pulse Skip Threshold V In pulse skip mode 0.9 V COMP,THRES COMPx Clamp High Voltage V 2.25 V COMP,HIGH THERMAL SHUTDOWN Thermal Shutdown Threshold T 155 TMSD °C Thermal Shutdown Hysteresis 20 °C OVERVOLTAGE AND POWER GOOD THRESHOLDS FBx Overvoltage Threshold V V rising 0.635 0.65 0.665 V OV FB FBx Overvoltage Hysteresis 30 mV FBx Undervoltage Threshold V V falling 0.525 0.55 0.578 V UV FB FBx Undervoltage Hysteresis 30 mV TRKx INPUT VOLTAGE RANGE 0 5 V FBx TO TRKx OFFSET VOLTAGE TRKx = 0.1 V to 0.57 V, offset = V − V −10 0 +10 mV FB TRK SOFT START SSx Output Current I During start-up 4.6 6.5 8.4 µA SS SSx Pull-Down Resistor During a fault condition 3 kΩ FBx to SSx Offset V = 0.1 V to 0.6 V, offset = V − V −10 +10 mV SS FB SS PGOODx PGOODx Pull-up Resistor R Internal pull-up resistor to VCCO 12.5 kΩ PGOOD PGOODx Delay 12 µs Over Voltage or Under Voltage This is the minimum duration required to trip 10 µs the PGOOD signal Minimum Duration ILIM1, ILIM2 Threshold Voltage1 Relative to PGNDx −5 0 +5 mV ILIM1, ILIM2 Output Current ILIMx = PGNDx 47 50 53 µA Current Sense Blanking Period After DLx goes high, current limit is not sensed 100 ns during this period INTEGRATED RECTIFIER At 20 mA forward current 16 Ω (BOOST DIODE) RESISTANCE ZERO CURRENT CROSS OFFSET In pulse skip mode only, f = 600 kHz 0 2 4 mV SW (SWx TO PGNDx)1 1 Guaranteed by design. 2 Connect VIN to VCCO when 2.75 V < VIN < 5.5 V. Rev. C | Page 4 of 32 Document Outline Features Applications General Description Typical Operation Circuit Revision History Specifications Absolute Maximum Ratings ESD Caution Simplified Block Diagram Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Control Architecture Oscillator Frequency Modes of Operation Synchronization Synchronous Rectifier and Dead Time Input Undervoltage Lockout Internal Linear Regulator Overvoltage Protection Power Good Short-Circuit and Current-Limit Protection Shutdown Control Thermal Overload Protection Applications Information Setting the Output Voltage Soft Start Setting the Current Limit Accurate Current-Limit Sensing Setting the Slope Compensation Setting the Current Sense Gain Input Capacitor Selection Input Filter Boost Capacitor Selection Inductor Selection Output Capacitor Selection MOSFET Selection Loop Compensation (Single Phase Operation) Configuration and Loop Compensation (Dual-Phase Operation) Switching Noise and Overshoot Reduction Voltage Tracking Coincident Tracking Ratiometric Tracking Indepdendent Power Stage Input Voltage PCB Layout Guidelines MOSFETs, Input Bulk Capacitor, and Bypass Capacitor High Current and Current Sense Paths Signal Paths PGND Plane Feedback and Current-Limit Sense Paths Switch Node Gate Driver Paths Output Capacitors Typical Operating Circuits Outline Dimensions Ordering Guide