Datasheet LTC3802 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | Dual 550kHz Synchronous 2-Phase DC/DC Controller with Programmable Up/Down Tracking |
| Pages / Page | 28 / 10 — PI FU CTIO S (28-Pin SSOP/32-Pin QFN Package). PHASEMD (Pin 17/Pin 15):. … |
| File Format / Size | PDF / 359 Kb |
| Document Language | English |
PI FU CTIO S (28-Pin SSOP/32-Pin QFN Package). PHASEMD (Pin 17/Pin 15):. IMAX2 (Pin 22/Pin 20):. PLLLPF (Pin 23/Pin 21):
Model Line for this Datasheet
Text Version of Document
LTC3802
U U U PI FU CTIO S (28-Pin SSOP/32-Pin QFN Package) PHASEMD (Pin 17/Pin 15):
Phase Selector Input. This pin
IMAX2 (Pin 22/Pin 20):
Channel 2 Controller Current Limit determines the phase relationships between controller␣ 1, Set. See IMAX1. controller 2 and the PLLIN signal. When PHASEMD is
PLLLPF (Pin 23/Pin 21):
Phase-Locked Loop Lowpass floating, its value is around 2V, and the internal phase- Filter. The phase-locked loop’s lowpass filter is tied to this locked loop synchronizes the falling edge of TG1 to the pin. Alternatively, this pin can be driven with an AC or DC falling edge of the PLLIN signal. When PHASEMD is forced voltage source to vary the frequency of the internal high, PLLIN leads TG1 by 90°. TG1 and TG2 remain at 180° oscillator. out of phase independent of the PHASEMD input. When PHASEMD is forced low, an internal current source dis-
PLLIN (Pin 24/Pin 22):
Phase-Locked Loop Input/Exter- charges the RUN/SS slowly to provide power down track- nal Synchronization Input to the Phase Detector. The ing. Avoid coupling noise into this sensitive pin. falling edge of this signal is used for frequency synchro- nization. When PLLIN floats or shorts to ground, the
FB2 (Pin 18/Pin 16):
Channel 2 Controller Error Amplifier controllers free run at 550kHz. Input. See FB1.
SW2 (Pin 25/Pin 25):
Channel 2 Controller Switching
COMP2 (Pin 19/Pin 17):
Channel 2 Controller Error Am- Node. See SW1. plifier Output. See COMP1.
TG2 (Pin 26/Pin 26):
Channel 2 Controller Top Gate Drive.
VCC (Pin 20/Pin 18):
Power Supply Input. All the internal See TG1. circuits except the switcher output drivers are powered from this pin. V
BOOST2 (Pin 27/Pin 27):
Channel 2 Controller Top Gate CC should be connected to a low noise 5V supply and should be bypassed to SGND with at least a Driver Supply. See BOOST1. 10µF capacitor in close proximity to the LTC3802.
BG2 (Pin 28/Pin 28):
Channel 2 Controller Bottom Gate
CMPIN2 (Pin 21/Pin 19):
Channel 2 Controller Compara- Drive. See BG1. tors Input. See CMPIN1.
Exposed Pad (Pin 33, QFN Package Only):
Exposed Pad is PGND, must be soldered to PCB. 3802f 10
U U U PI FU CTIO S (28-Pin SSOP/32-Pin QFN Package) PHASEMD (Pin 17/Pin 15):
Phase Selector Input. This pin
IMAX2 (Pin 22/Pin 20):
Channel 2 Controller Current Limit determines the phase relationships between controller␣ 1, Set. See IMAX1. controller 2 and the PLLIN signal. When PHASEMD is
PLLLPF (Pin 23/Pin 21):
Phase-Locked Loop Lowpass floating, its value is around 2V, and the internal phase- Filter. The phase-locked loop’s lowpass filter is tied to this locked loop synchronizes the falling edge of TG1 to the pin. Alternatively, this pin can be driven with an AC or DC falling edge of the PLLIN signal. When PHASEMD is forced voltage source to vary the frequency of the internal high, PLLIN leads TG1 by 90°. TG1 and TG2 remain at 180° oscillator. out of phase independent of the PHASEMD input. When PHASEMD is forced low, an internal current source dis-
PLLIN (Pin 24/Pin 22):
Phase-Locked Loop Input/Exter- charges the RUN/SS slowly to provide power down track- nal Synchronization Input to the Phase Detector. The ing. Avoid coupling noise into this sensitive pin. falling edge of this signal is used for frequency synchro- nization. When PLLIN floats or shorts to ground, the
FB2 (Pin 18/Pin 16):
Channel 2 Controller Error Amplifier controllers free run at 550kHz. Input. See FB1.
SW2 (Pin 25/Pin 25):
Channel 2 Controller Switching
COMP2 (Pin 19/Pin 17):
Channel 2 Controller Error Am- Node. See SW1. plifier Output. See COMP1.
TG2 (Pin 26/Pin 26):
Channel 2 Controller Top Gate Drive.
VCC (Pin 20/Pin 18):
Power Supply Input. All the internal See TG1. circuits except the switcher output drivers are powered from this pin. V
BOOST2 (Pin 27/Pin 27):
Channel 2 Controller Top Gate CC should be connected to a low noise 5V supply and should be bypassed to SGND with at least a Driver Supply. See BOOST1. 10µF capacitor in close proximity to the LTC3802.
BG2 (Pin 28/Pin 28):
Channel 2 Controller Bottom Gate
CMPIN2 (Pin 21/Pin 19):
Channel 2 Controller Compara- Drive. See BG1. tors Input. See CMPIN1.
Exposed Pad (Pin 33, QFN Package Only):
Exposed Pad is PGND, must be soldered to PCB. 3802f 10
