Datasheet ADSP-BF522, ADSP-BF523, ADSP-BF524, ADSP-BF525, ADSP-BF526, ADSP-BF527 (Analog Devices) - 5

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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
length, and base registers (for circular buffering), and eight
0xFFFF FFFF
additional 32-bit pointer registers (for C-style indexed stack
CORE MMR REGISTERS (2M BYTES)
manipulation).
0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000
Blackfin processors support a modified Harvard architecture in
RESERVED
combination with a hierarchical memory structure. Level 1 (L1)
0xFFB0 1000 SCRATCHPAD SRAM (4K BYTES)
memories are those that typically operate at the full processor
0xFFB0 0000
speed with little or no latency. At the L1 level, the instruction
RESERVED 0xFFA1 4000
memory holds instructions only. The two data memories hold
INSTRUCTION SRAM / CACHE (16K BYTES)
data, and a dedicated scratchpad data memory stores stack and
0xFFA1 0000 RESERVED AP
local variable information.
0xFFA0 C000 M INSTRUCTION BANK B SRAM (16K BYTES) Y
In addition, multiple L1 memory blocks are provided, offering a
R 0xFFA0 8000 O INSTRUCTION BANK A SRAM (32K BYTES)
configurable mix of SRAM and cache. The memory manage-
EM 0xFFA0 0000 M
ment unit (MMU) provides memory protection for individual
RESERVED L 0xFF90 8000 A
tasks that may be operating on the core and can protect system
DATA BANK B SRAM / CACHE (16K BYTES) N ER 0xFF90 4000
registers from unintended access.
T DATA BANK B SRAM (16K BYTES) IN 0xFF90 0000
The architecture provides three modes of operation: user mode,
RESERVED
supervisor mode, and emulation mode. User mode has
0xFF80 8000 DATA BANK A SRAM / CACHE (16K BYTES)
restricted access to certain system resources, thus providing a
0xFF80 4000 DATA BANK A SRAM (16K BYTES)
protected software environment, while supervisor mode has
0xFF80 0000
unrestricted access to the system and core resources.
RESERVED 0xEF00 8000
The Blackfin processor instruction set has been optimized so
BOOT ROM (32K BYTES) 0xEF00 0000
that 16-bit opcodes represent the most frequently used instruc-
P RESERVED A
tions, resulting in excellent compiled code density. Complex
0x2040 0000 M ASYNC MEMORY BANK 3 (1M BYTES) Y R
DSP instructions are encoded into 32-bit opcodes, representing
0x2030 0000 O ASYNC MEMORY BANK 2 (1M BYTES) M
fully featured multifunction instructions. Blackfin processors
E 0x2020 0000 M
support a limited multi-issue capability, where a 32-bit instruc-
ASYNC MEMORY BANK 1 (1M BYTES) L 0x2010 0000 NA
tion can be issued in parallel with two 16-bit instructions,
ASYNC MEMORY BANK 0 (1M BYTES) R
allowing the programmer to use many of the core resources in a
0x2000 0000 TE X RESERVED E
single instruction cycle.
0x08 00 0000 SDRAM MEMORY (16M BYTES 128M BYTES)
The Blackfin processor assembly language uses an algebraic syn-
0x0000 0000
tax for ease of coding and readability. The architecture has been Figure 3. Internal/External Memory Map optimized for use in conjunction with the C/C++ compiler, resulting in fast and efficient software implementations.
Internal (On-Chip) Memory MEMORY ARCHITECTURE
The processor has three blocks of on-chip memory providing high-bandwidth access to the core. The Blackfin processor views memory as a single unified 4G byte address space, using 32-bit addresses. All resources, The first block is the L1 instruction memory, consisting of including internal memory, external memory, and I/O control 64K bytes SRAM, of which 16K bytes can be configured as a registers, occupy separate sections of this common address four-way set-associative cache. This memory is accessed at full space. The memory portions of this address space are arranged processor speed. in a hierarchical structure to provide a good cost/performance The second on-chip memory block is the L1 data memory, con- balance of some very fast, low-latency on-chip memory as cache sisting of up to two banks of up to 32K bytes each. Each memory or SRAM, and larger, lower-cost and performance off-chip bank is configurable, offering both cache and SRAM functional- memory systems. See Figure 3. ity. This memory block is accessed at full processor speed. The on-chip L1 memory system is the highest-performance The third memory block is a 4K byte scratchpad SRAM which memory available to the Blackfin processor. The off-chip runs at the same speed as the L1 memories, but is only accessible memory system, accessed through the external bus interface as data SRAM and cannot be configured as cache memory. unit (EBIU), provides expansion with SDRAM, flash memory, and SRAM, optionally accessing up to 132M bytes of
External (Off-Chip) Memory
physical memory. External memory is accessed via the EBIU. This 16-bit interface The memory DMA controller provides high-bandwidth data- provides a glueless connection to a bank of synchronous DRAM movement capability. It can perform block transfers of code (SDRAM), as well as up to four banks of asynchronous memory or data between the internal memory and the external devices including flash, EPROM, ROM, SRAM, and memory memory spaces. mapped I/O devices. Rev. D | Page 5 of 88 | July 2013 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory NAND Flash Controller (NFC) One-Time Programmable Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Host DMA Port Real-Time Clock Watchdog Timer Timers Up/Down Counter and Thumbwheel Interface Serial Ports Serial Peripheral Interface (SPI) Port UART Ports TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode USB On-The-Go Dual-Role Device Controller Code Security with Lockbox Secure Technology Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage Regulation ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Lockbox Secure Technology Disclaimer Signal Descriptions Specifications Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Clock Related Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Clock Related Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors Electrical Characteristics Total Power Dissipation Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing NAND Flash Controller Interface Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port—Master Timing Serial Peripheral Interface (SPI) Port—Slave Timing Universal Serial Bus (USB) On-The-Go—Receive and Transmit Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing General-Purpose Port Timing Timer Cycle Timing Timer Clock Timing Up/Down Counter/Rotary Encoder Timing HOSTDP A/C Timing- Host Read Cycle HOSTDP A/C Timing- Host Write Cycle 10/100 Ethernet MAC Controller Timing JTAG Test And Emulation Port Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 289-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide