Datasheet ADSP-BF534, ADSP-BF536, ADSP-BF537 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | Blackfin Embedded Processor |
| Pages / Page | 68 / 2 — ADSP-BF534/ADSP-BF536/ADSP-BF537. TABLE OF CONTENTS. REVISION HISTORY. … |
| Revision | J |
| File Format / Size | PDF / 2.4 Mb |
| Document Language | English |
ADSP-BF534/ADSP-BF536/ADSP-BF537. TABLE OF CONTENTS. REVISION HISTORY. 2/14—Rev. I to Rev. J
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ADSP-BF534/ADSP-BF536/ADSP-BF537 TABLE OF CONTENTS
Features ... 1 Booting Modes ... 16 Memory .. 1 Instruction Set Description .. 17 Peripherals ... 1 Development Tools .. 17 General Description ... 3 Additional Information .. 18 Portable Low Power Architecture ... 3 Related Signal Chains ... 18 System Integration .. 3 Pin Descriptions .. 19 Blackfin Processor Peripherals ... 3 Specifications .. 23 Blackfin Processor Core .. 4 Operating Conditions ... 23 Memory Architecture .. 5 Electrical Characteristics ... 25 DMA Controllers .. 8 Absolute Maximum Ratings ... 29 Real-Time Clock ... 9 ESD Sensitivity ... 29 Watchdog Timer .. 9 Package Information .. 29 Timers ... 9 Timing Specifications ... 30 Serial Ports (SPORTs) .. 10 Output Drive Currents ... 50 Serial Peripheral Interface (SPI) Port ... 10 Test Conditions .. 52 UART Ports .. 10 Thermal Characteristics .. 56 Controller Area Network (CAN) .. 11 182-Ball CSP_BGA Ball Assignment ... 57 TWI Controller Interface .. 11 208-Ball CSP_BGA Ball Assignment ... 60 10/100 Ethernet MAC .. 11 Outline Dimensions .. 63 Ports .. 12 Surface-Mount Design .. 65 Parallel Peripheral Interface (PPI) ... 12 Automotive Products .. 66 Dynamic Power Management .. 13 Ordering Guide ... 67 Voltage Regulation .. 14 Clock Signals ... 15
REVISION HISTORY 2/14—Rev. I to Rev. J
Corrected typographical error from Three 16-bit MACs to Two 16-bit MACs in Features .. 1 Updated Development Tools .. 17 Added tHDRE parameter to Serial Port Timing .. 38 Added footnotes in Serial Port Timing .. 38 Rev. J | Page 2 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
ADSP-BF534/ADSP-BF536/ADSP-BF537 TABLE OF CONTENTS
Features ... 1 Booting Modes ... 16 Memory .. 1 Instruction Set Description .. 17 Peripherals ... 1 Development Tools .. 17 General Description ... 3 Additional Information .. 18 Portable Low Power Architecture ... 3 Related Signal Chains ... 18 System Integration .. 3 Pin Descriptions .. 19 Blackfin Processor Peripherals ... 3 Specifications .. 23 Blackfin Processor Core .. 4 Operating Conditions ... 23 Memory Architecture .. 5 Electrical Characteristics ... 25 DMA Controllers .. 8 Absolute Maximum Ratings ... 29 Real-Time Clock ... 9 ESD Sensitivity ... 29 Watchdog Timer .. 9 Package Information .. 29 Timers ... 9 Timing Specifications ... 30 Serial Ports (SPORTs) .. 10 Output Drive Currents ... 50 Serial Peripheral Interface (SPI) Port ... 10 Test Conditions .. 52 UART Ports .. 10 Thermal Characteristics .. 56 Controller Area Network (CAN) .. 11 182-Ball CSP_BGA Ball Assignment ... 57 TWI Controller Interface .. 11 208-Ball CSP_BGA Ball Assignment ... 60 10/100 Ethernet MAC .. 11 Outline Dimensions .. 63 Ports .. 12 Surface-Mount Design .. 65 Parallel Peripheral Interface (PPI) ... 12 Automotive Products .. 66 Dynamic Power Management .. 13 Ordering Guide ... 67 Voltage Regulation .. 14 Clock Signals ... 15
REVISION HISTORY 2/14—Rev. I to Rev. J
Corrected typographical error from Three 16-bit MACs to Two 16-bit MACs in Features .. 1 Updated Development Tools .. 17 Added tHDRE parameter to Serial Port Timing .. 38 Added footnotes in Serial Port Timing .. 38 Rev. J | Page 2 of 68 | February 2014 Document Outline Blackfin Embedded Processor Features Memory Peripherals Table Of Contents Revision History General Description Portable Low Power Architecture System Integration Blackfin Processor Peripherals Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Real-Time Clock Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Ports Controller Area Network (CAN) TWI Controller Interface 10/100 Ethernet MAC Ports General-Purpose I/O (GPIO) Parallel Peripheral Interface (PPI) General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode—Maximum Performance Active Operating Mode—Moderate Dynamic Power Savings Sleep Operating Mode—High Dynamic Power Savings Deep Sleep Operating Mode—Maximum Dynamic Power Savings Hibernate State—Maximum Static Power Savings Power Savings Voltage Regulation Clock Signals Booting Modes Instruction Set Description Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings ESD Sensitivity Package Information Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing External Port Bus Request and Grant Cycle Timing SDRAM Interface Timing External DMA Request Timing Parallel Peripheral Interface Timing Serial Port Timing Serial Peripheral Interface Port—Master Timing Serial Peripheral Interface Port—Slave Timing General-Purpose Port Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Timer Clock Timing Timer Cycle Timing JTAG Test and Emulation Port Timing 10/100 Ethernet MAC Controller Timing Output Drive Currents Test Conditions Output Enable Time Output Disable Time Example System Hold Time Calculation Capacitive Loading Thermal Characteristics 182-Ball CSP_BGA Ball Assignment 208-Ball CSP_BGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide
