Datasheet AD5116 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | Single-Channel, 64-Position, Push Button, ±8% Resistor Tolerance, Nonvolatile Digital Potentiometer |
| Pages / Page | 16 / 5 — Data Sheet. AD5116. INTERFACE TIMING SPECIFICATIONS. Table 3. Parameter. … |
| Revision | B |
| File Format / Size | PDF / 377 Kb |
| Document Language | English |
Data Sheet. AD5116. INTERFACE TIMING SPECIFICATIONS. Table 3. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit. Description
Model Line for this Datasheet
Text Version of Document
link to page 5 link to page 5
Data Sheet AD5116 INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Test Conditions/Comments Min Typ Max Unit Description
t 8 ms Debounce time 1 t 1 sec Manual to auto scan time 2 t 140 ms Auto scan step 3 t 4 ASE = 0 V, PD = GND, PU = GND 1 sec Auto save execute time t 8 ms Low pulse time to manual storage 5 ASE = VDD t 1 15 50 ms Memory program time EEPROM_PROGRAM t 2 50 µs Power-on EEPROM restore time POWER_UP 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. 2 Maximum time after VDD is equal to 2.3 V.
TIMING DIAGRAMS PD/PU (LOW) t1 t tEEPROM 5 PROGRAM PU ASE PD (LOW) R EEPROM DATA NEW DATA W
002 005 09657- 09657- Figure 2. Manual Increment Mode Timing Figure 5. Manual Save Mode Timing
t1 t t 1 3 PD PU t2 RW = 45Ω R PD (LOW) W RW
003 006
ASE
09657- 09657- Figure 3. Auto Increment Mode Timing Figure 6. End Scale Indication Timing
t1 t tEEPROM 4 PROGRAM PD RW ASE (LOW) EEPROM DATA NEW DATA
004 09657- Figure 4. Auto Save Mode Timing Rev. B | Page 5 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Interface Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation RDAC Register Manual Increment Auto Scan Increment Low Wiper Resistance Feature EEPROM Automatic Save Enable Auto Save Manual Store End Scale Resistance Indicator RDAC Architecture Top Scale/Bottom Scale Architecture Programming the Variable Resistor Rheostat Operation—±8% Resistor Tolerance Programming the Potentiometer Divider Voltage Output Operation Terminal Voltage Operating Range Power-Up Sequence Layout and Power Supply Biasing Outline Dimensions Ordering Guide
Data Sheet AD5116 INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3. Parameter Test Conditions/Comments Min Typ Max Unit Description
t 8 ms Debounce time 1 t 1 sec Manual to auto scan time 2 t 140 ms Auto scan step 3 t 4 ASE = 0 V, PD = GND, PU = GND 1 sec Auto save execute time t 8 ms Low pulse time to manual storage 5 ASE = VDD t 1 15 50 ms Memory program time EEPROM_PROGRAM t 2 50 µs Power-on EEPROM restore time POWER_UP 1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at a lower temperature and higher write cycles. 2 Maximum time after VDD is equal to 2.3 V.
TIMING DIAGRAMS PD/PU (LOW) t1 t tEEPROM 5 PROGRAM PU ASE PD (LOW) R EEPROM DATA NEW DATA W
002 005 09657- 09657- Figure 2. Manual Increment Mode Timing Figure 5. Manual Save Mode Timing
t1 t t 1 3 PD PU t2 RW = 45Ω R PD (LOW) W RW
003 006
ASE
09657- 09657- Figure 3. Auto Increment Mode Timing Figure 6. End Scale Indication Timing
t1 t tEEPROM 4 PROGRAM PD RW ASE (LOW) EEPROM DATA NEW DATA
004 09657- Figure 4. Auto Save Mode Timing Rev. B | Page 5 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Interface Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation RDAC Register Manual Increment Auto Scan Increment Low Wiper Resistance Feature EEPROM Automatic Save Enable Auto Save Manual Store End Scale Resistance Indicator RDAC Architecture Top Scale/Bottom Scale Architecture Programming the Variable Resistor Rheostat Operation—±8% Resistor Tolerance Programming the Potentiometer Divider Voltage Output Operation Terminal Voltage Operating Range Power-Up Sequence Layout and Power Supply Biasing Outline Dimensions Ordering Guide
