Datasheet ADSP-21371, ADSP-21375 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | SHARC Processor |
| Pages / Page | 56 / 3 — ADSP-21371. /ADSP-21375. GENERAL DESCRIPTION. Table 2. … |
| Revision | D |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
ADSP-21371. /ADSP-21375. GENERAL DESCRIPTION. Table 2. ADSP-21371/ADSP-21375 Features (Continued). Feature. ADSP-21375
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ADSP-21371 /ADSP-21375 GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC® processors are mem-
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
bers of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source
Feature ADSP-21371 ADSP-21375
code compatible with the ADSP-2126x, ADSP-2136x, and Digital Peripheral Interface Yes ADSP-2116x DSPs, as well as with first generation ADSP-2106x (DPI) SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point proces- S/PDIF Transceiver Yes No sors optimized for high performance automotive audio SPI 2 applications with their large on-chip SRAM and mask-pro- grammable ROM, multiple internal buses to eliminate I/O TWI Yes bottlenecks, and an innovative digital applications interface Package 208-Lead LQFP_EP (DAI). As shown in the functional block diagram on Page 1, the pro- The diagram on Page 1 shows the two clock domains that make cessors use two computational units to deliver a significant up the ADSP-2137x processors. The core clock domain contains performance increase over the previous SHARC processors on a the following features: range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processors achieve an instruction • Two processing elements, each of which comprises an cycle time of 3.75 ns at 266 MHz. With its SIMD computational ALU, multiplier, shifter, and data register file hardware, the processors can perform 1.596 GFLOPS running • Data address generators (DAG1, DAG2) at 266 MHz. • Program sequencer with instruction cache Table 1 shows performance benchmarks for these devices. • PM and DM buses capable of supporting four 32-bit data Table 2 shows the features of the individual product offerings. transfers between memory and the core at every core pro- cessor cycle
Table 1. Processor Benchmarks (at 266 MHz)
• One periodic interval timer with pinout
Speed
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
Benchmark Algorithm (at 266 MHz)
ADSP-21375) 1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s • On-chip mask-programmable ROM (4M bit, ADSP-21371; FIR Filter (per Tap)1 1.88 ns 2M bit, ADSP-21375) IIR Filter (per Biquad)1 7.5 ns • JTAG test access port for emulation and boundary scan. Matrix Multiply (Pipelined) The JTAG provides software debug through user break- [3 × 3] × [3 × 1] 16.91 ns points which allow flexible exception handling. [4 × 4] × [4 × 1] 30.07 ns The diagram on Page 1 also shows the peripheral clock domains Divide (y/x) 13.1 ns (also known as the I/O processor) and contains the following Inverse Square Root 20.4 ns features: 1 Assumes two files in multichannel SIMD mode • IOD0 (periphera l DMA) and IOD1 (external port DMA) buses for 32-bit data transfers
Table 2. ADSP-21371/ADSP-21375 Features
• Peripheral and external port bus for core connection • Digital applications interface that includes four precision
Feature ADSP-21371 ADSP-21375
clock generators (PCG), an S/PDIF-compatible digital Frequency 266 MHz 266 MHz audio receiver/transmitter, an input data port (IDP), eight (3.75 ns) (3.75 ns) serial ports, eight serial interfaces, a 20-bit parallel input RAM 1M bit 0.5M bit port (PDAP), and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, one ROM 4M bits 2M bits UART, two serial peripheral interfaces (SPI), a 2-wire Pulse-Width Modulation Yes No interface (TWI), and a flexible signal routing unit Serial Ports 8 4 (DPI SRU). • External port with AMI and SDRAM controller UART 1 • Four units for PWM control Digital Application Yes Interface (DAI) • One MTM for internal to internal memory transfers Rev. D | Page 3 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide
ADSP-21371 /ADSP-21375 GENERAL DESCRIPTION
The ADSP-21371/ADSP-21375 SHARC® processors are mem-
Table 2. ADSP-21371/ADSP-21375 Features (Continued)
bers of the SIMD SHARC family of DSPs that feature Analog Devices’ Super Harvard Architecture. The processors are source
Feature ADSP-21371 ADSP-21375
code compatible with the ADSP-2126x, ADSP-2136x, and Digital Peripheral Interface Yes ADSP-2116x DSPs, as well as with first generation ADSP-2106x (DPI) SHARC processors in SISD (single-instruction, single-data) mode. The processors are 32-bit/40-bit floating-point proces- S/PDIF Transceiver Yes No sors optimized for high performance automotive audio SPI 2 applications with their large on-chip SRAM and mask-pro- grammable ROM, multiple internal buses to eliminate I/O TWI Yes bottlenecks, and an innovative digital applications interface Package 208-Lead LQFP_EP (DAI). As shown in the functional block diagram on Page 1, the pro- The diagram on Page 1 shows the two clock domains that make cessors use two computational units to deliver a significant up the ADSP-2137x processors. The core clock domain contains performance increase over the previous SHARC processors on a the following features: range of DSP algorithms. Fabricated in a state-of-the-art, high speed, CMOS process, the processors achieve an instruction • Two processing elements, each of which comprises an cycle time of 3.75 ns at 266 MHz. With its SIMD computational ALU, multiplier, shifter, and data register file hardware, the processors can perform 1.596 GFLOPS running • Data address generators (DAG1, DAG2) at 266 MHz. • Program sequencer with instruction cache Table 1 shows performance benchmarks for these devices. • PM and DM buses capable of supporting four 32-bit data Table 2 shows the features of the individual product offerings. transfers between memory and the core at every core pro- cessor cycle
Table 1. Processor Benchmarks (at 266 MHz)
• One periodic interval timer with pinout
Speed
• On-chip SRAM (1M bit, ADSP-21371; 0.5M bit,
Benchmark Algorithm (at 266 MHz)
ADSP-21375) 1024 Point Complex FFT (Radix 4, With Reversal) 34.5 s • On-chip mask-programmable ROM (4M bit, ADSP-21371; FIR Filter (per Tap)1 1.88 ns 2M bit, ADSP-21375) IIR Filter (per Biquad)1 7.5 ns • JTAG test access port for emulation and boundary scan. Matrix Multiply (Pipelined) The JTAG provides software debug through user break- [3 × 3] × [3 × 1] 16.91 ns points which allow flexible exception handling. [4 × 4] × [4 × 1] 30.07 ns The diagram on Page 1 also shows the peripheral clock domains Divide (y/x) 13.1 ns (also known as the I/O processor) and contains the following Inverse Square Root 20.4 ns features: 1 Assumes two files in multichannel SIMD mode • IOD0 (periphera l DMA) and IOD1 (external port DMA) buses for 32-bit data transfers
Table 2. ADSP-21371/ADSP-21375 Features
• Peripheral and external port bus for core connection • Digital applications interface that includes four precision
Feature ADSP-21371 ADSP-21375
clock generators (PCG), an S/PDIF-compatible digital Frequency 266 MHz 266 MHz audio receiver/transmitter, an input data port (IDP), eight (3.75 ns) (3.75 ns) serial ports, eight serial interfaces, a 20-bit parallel input RAM 1M bit 0.5M bit port (PDAP), and a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes two timers, one ROM 4M bits 2M bits UART, two serial peripheral interfaces (SPI), a 2-wire Pulse-Width Modulation Yes No interface (TWI), and a flexible signal routing unit Serial Ports 8 4 (DPI SRU). • External port with AMI and SDRAM controller UART 1 • Four units for PWM control Digital Application Yes Interface (DAI) • One MTM for internal to internal memory transfers Rev. D | Page 3 of 56 | April 2013 Document Outline Summary Dedicated Audio Components Table Of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of an Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Code Execution External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Input Data Port (IDP) Precision Clock Generator (PCG) Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA Scatter/Gather DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions ADSP-21371/ADSP-21375 Specifications Operating Conditions Electrical Characteristics Package Information Maximum Power Dissipation Absolute Maximum Ratings ESD Sensitivity Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Running Reset Core Timer Interrupts Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing Memory Read—Bus Master Memory Write—Bus Master Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators (PWM) S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (HFCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave Universal Asynchronous Receiver-Transmitter (UART) Port—Receive and Transmit Timing TWI Controller Timing JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 208-Lead LQFP_EP Pinout Package Dimensions Automotive Products Ordering Guide
