Datasheet Si8941/46/47 (Silicon Labs) - 9
| Manufacturer | Silicon Labs |
| Description | Isolated Delta-Sigma Modulator for Current Shunt Measurement |
| Pages / Page | 35 / 9 — Parameter. Symbol. Test Condition. Min. Typ. Max. Units. Digital. … |
| Revision | 0.5 |
| File Format / Size | PDF / 542 Kb |
| Document Language | English |
Parameter. Symbol. Test Condition. Min. Typ. Max. Units. Digital. External Clock (Si8941). Internal Clock (Si8946). Internal Clock (Si8947)
Model Line for this Datasheet
Text Version of Document
link to page 6 Si8941/46/47 Data Sheet Electrical Specifications
Parameter Symbol Test Condition Min Typ Max Units
PSRR vs. VDDA at DC –100 dB PSRR vs. VDDA at 100 –100 dB mV and 10 kHz ripple Power-Supply Rejection Ratio PSRR PSRR vs. VDDB at DC –100 dB PSRR vs. VDDB at 100 –100 dB mV and 10 kHz ripple Common-Mode Transient Immunity CMTI 50 75 kV/µs
Digital
70% of Logic high input threshold VIH V VDDB 20% of Logic low input threshold VIL V VDDB Input hysteresis VIHYST 120 mV Output load capacitance CLOAD 15 pF
External Clock (Si8941)
Clock Frequency FCLKIN 5 25 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 23 ns Data Hold Time THOLD 6 ns
Internal Clock (Si8946)
TA = 25 °C 9.9 10 10.1 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 9.8 10 10.2 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 60 ns Data Hold Time THOLD 40 ns
Internal Clock (Si8947)
TA = 25 °C 19.8 20 20.2 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 19.6 20 20.4 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 30 ns Data Hold Time THOLD 20 ns
Note:
1. Average value of VCM = 0 with example circuit shown in Figure 3.1 Current Sense Application on page 6.
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 9 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
Parameter Symbol Test Condition Min Typ Max Units
PSRR vs. VDDA at DC –100 dB PSRR vs. VDDA at 100 –100 dB mV and 10 kHz ripple Power-Supply Rejection Ratio PSRR PSRR vs. VDDB at DC –100 dB PSRR vs. VDDB at 100 –100 dB mV and 10 kHz ripple Common-Mode Transient Immunity CMTI 50 75 kV/µs
Digital
70% of Logic high input threshold VIH V VDDB 20% of Logic low input threshold VIL V VDDB Input hysteresis VIHYST 120 mV Output load capacitance CLOAD 15 pF
External Clock (Si8941)
Clock Frequency FCLKIN 5 25 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 23 ns Data Hold Time THOLD 6 ns
Internal Clock (Si8946)
TA = 25 °C 9.9 10 10.1 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 9.8 10 10.2 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 60 ns Data Hold Time THOLD 40 ns
Internal Clock (Si8947)
TA = 25 °C 19.8 20 20.2 MHz Clock Frequency FCLKOUT TA = –40 °C to 125 °C 19.6 20 20.4 MHz Duty Cycle FDUTY 45 50 55 % Delay to Data Valid TDELAY 30 ns Data Hold Time THOLD 20 ns
Note:
1. Average value of VCM = 0 with example circuit shown in Figure 3.1 Current Sense Application on page 6.
silabs.com
| Building a more connected world. Preliminary Rev. 0.5 | 9 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Current Sense Application 4. Electrical Specifications 4.1 Regulatory Information 4.2 Typical Operating Characteristics 5. Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Revision History
