Datasheet STSPIN32F0B (STMicroelectronics) - 3
| Manufacturer | STMicroelectronics |
| Description | Advanced single shunt BLDC controller with embedded STM32 MCU |
| Pages / Page | 36 / 3 — STSPIN32F0B. Block diagrams. Figure 2. STSPIN32F0B System-In-Package … |
| File Format / Size | PDF / 6.5 Mb |
| Document Language | English |
STSPIN32F0B. Block diagrams. Figure 2. STSPIN32F0B System-In-Package block diagram. VREG1. COMP. ADJ REF. OPAMP. 3.3V. 32F031. STM. DS12907
Model Line for this Datasheet
Text Version of Document
STSPIN32F0B Block diagrams 2 Block diagrams Figure 2. STSPIN32F0B System-In-Package block diagram
U V W T T T O U O V O W O U O V O W S UT U S UT V S UT W VB H O LS VB H O LS VB H O LS
2 2 2 S S S VREG1 LS H VREG1 LS H VREG1 LS H 2 2 2 VREG1 VREG1 VREG1 2 VREG1
Control Logic OC_COMP
COMP
VREG 12V Gate Driver
ADJ REF
EG
VM
12V VR 2 6 OP1P
OPAMP
SW OP1N OP1O C Buck conv VM C/D
VM
OC_SEL p threshold select control D
3.3V
C com to VDDA O PA13_SWD_IO RESERVED
3.3V
RESERVED RESERVED GND connected to EPAD PF7 PF6 PA13 PA12 PA11 PA10 PB12 PA9 PA8 PB14 PB13 PB15 PA14_SWD_CLK PA14 TEST MODE PA15 PA15 PB3 VDD PB4 VSS PB5 PB6 PB11 PB6 PB10 PB7 PB7 PB2 BOOT0 PB8
32F031
BOOT0 PB9 PB1 PB1 VSS
STM
PB0 PA7 PA7 VDD PA6 PA6 PB8 VBAT PA5 PA4 PA5 PB9 A RST D PA4 PC13 PC14 PC15 PF0 PF1 N PA2 PA3 VSSA PA0 PA1 VD VDD A PF0 PF1 D PA0 PA1 PA2 PA3 PC14 PC15 NRST VD
DS12907
-
Rev 1 page 3/36
Document Outline 1 Description 2 Block diagrams 3 Electrical data 3.1 Absolute maximum ratings 3.2 ESD protections 3.3 Recommended operating conditions 3.4 Thermal data 4 Electrical characteristics 5 Pin description 6 Device description 6.1 UVLO and thermal protections 6.1.1 UVLO on supply voltages 6.1.2 Thermal protection 6.2 DC/DC buck regulator 6.2.1 External optional 3.3 V supply voltage 6.3 Linear regulator 6.4 Standby mode 6.5 Gate drivers 6.6 Microcontroller unit 6.6.1 Memories and boot mode 6.6.2 Power management 6.6.3 High-speed external clock source 6.6.4 Advanced-control timer (TIM1) 6.7 Test mode 6.8 Operational amplifier 6.9 Comparator 6.10 ESD protection strategy 7 Application example 8 Package information 8.1 VFQFPN48 7 x 7 package information Revision history Contents List of tables List of figures
U V W T T T O U O V O W O U O V O W S UT U S UT V S UT W VB H O LS VB H O LS VB H O LS
2 2 2 S S S VREG1 LS H VREG1 LS H VREG1 LS H 2 2 2 VREG1 VREG1 VREG1 2 VREG1
Control Logic OC_COMP
COMP
VREG 12V Gate Driver
ADJ REF
EG
VM
12V VR 2 6 OP1P
OPAMP
SW OP1N OP1O C Buck conv VM C/D
VM
OC_SEL p threshold select control D
3.3V
C com to VDDA O PA13_SWD_IO RESERVED
3.3V
RESERVED RESERVED GND connected to EPAD PF7 PF6 PA13 PA12 PA11 PA10 PB12 PA9 PA8 PB14 PB13 PB15 PA14_SWD_CLK PA14 TEST MODE PA15 PA15 PB3 VDD PB4 VSS PB5 PB6 PB11 PB6 PB10 PB7 PB7 PB2 BOOT0 PB8
32F031
BOOT0 PB9 PB1 PB1 VSS
STM
PB0 PA7 PA7 VDD PA6 PA6 PB8 VBAT PA5 PA4 PA5 PB9 A RST D PA4 PC13 PC14 PC15 PF0 PF1 N PA2 PA3 VSSA PA0 PA1 VD VDD A PF0 PF1 D PA0 PA1 PA2 PA3 PC14 PC15 NRST VD
DS12907
-
Rev 1 page 3/36
Document Outline 1 Description 2 Block diagrams 3 Electrical data 3.1 Absolute maximum ratings 3.2 ESD protections 3.3 Recommended operating conditions 3.4 Thermal data 4 Electrical characteristics 5 Pin description 6 Device description 6.1 UVLO and thermal protections 6.1.1 UVLO on supply voltages 6.1.2 Thermal protection 6.2 DC/DC buck regulator 6.2.1 External optional 3.3 V supply voltage 6.3 Linear regulator 6.4 Standby mode 6.5 Gate drivers 6.6 Microcontroller unit 6.6.1 Memories and boot mode 6.6.2 Power management 6.6.3 High-speed external clock source 6.6.4 Advanced-control timer (TIM1) 6.7 Test mode 6.8 Operational amplifier 6.9 Comparator 6.10 ESD protection strategy 7 Application example 8 Package information 8.1 VFQFPN48 7 x 7 package information Revision history Contents List of tables List of figures
