Datasheet A7987 (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | 61 V 3A asynchronous step-down switching regulator with adjustable current limitation for automotive |
| Pages / Page | 37 / 4 — A7987. Pin settings. 3.1. Pin connection. Figure 3. Pin connection (top … |
| File Format / Size | PDF / 1.4 Mb |
| Document Language | English |
A7987. Pin settings. 3.1. Pin connection. Figure 3. Pin connection (top view). 3.2. Pin description. Table 1. Pin description. Pin
Model Line for this Datasheet
Text Version of Document
A7987 Pin settings 3 Pin settings 3.1 Pin connection Figure 3. Pin connection (top view)
VBIAS 1 16 GND VIN 2 15 BOOT VIN 3 14 LX VCC 4 EXPOSED 13 LX PAD TO EN 5 SGND 12 PGOOD SS 6 11 ILIM SYNCH 7 10 FSW COMP 8 9 FB
3.2 Pin description Table 1. Pin description # Pin Description
Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency at light load. 1 VBIAS Typically connected to the regulated output voltage or to an external voltage rail higher than 3 V. Connect to GND if not used or bypass with a 1 µF ceramic capacitor if supplied by the output voltage or by an auxiliary rail. 2 VIN DC input voltage 3 VIN DC input voltage 4 VCC Filtered DC input voltage to the internal circuitry. Bypass to GND with a 1 µF ceramic capacitor. 5 EN Active high enable pin. Connect to VCC pin if not used. Soft-start programming pin. An internal current generator (5 µA typ.) charges the external capacitor to 6 SS implement the soft start. 7 SYNCH Master / slave synchronization 8 COMP Output of the error amplifier. The designed compensation network is connected at this pin. 9 FB Inverting input of the error amplifier. 10 FSW A pull down resistor to GND selects the switching frequency. 11 ILIM A pull down resistor to GND selects the peak current limitation. The PGOOD open collector output is driven low when the output voltage, sensed on the FB pin, is out of 12 PGOOD regulation. 13 LX Switching node 14 LX Switching node Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge required to drive the 15 BOOT internal n-DMOS is recovered by an internal regulator during the off-time.
DS12928
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Rev 1 page 4/37
Document Outline Cover image Product status link / summary Features Applications Description 1 Application schematic 2 Block diagram 3 Pin settings 3.1 Pin connection 3.2 Pin description 3.3 Maximum ratings 3.4 Thermal data 3.5 ESD protection 4 Electrical characteristics 5 Functional description 5.1 Oscillator and synchronization 5.2 Soft-start 5.3 Error amplifier and light-load management 5.4 Low VIN operation 5.5 Overcurrent protection 5.6 Overtemperature protection 6 Application information 6.1 Input capacitor selection 6.2 Output capacitor selection 6.3 Inductor selection 6.4 Compensation network 6.4.1 Type II compensation network 6.4.2 Type III compensation network 6.5 Thermal considerations 6.6 Layout considerations 7 Demonstration board 8 Application ideas 8.1 Positive buck-boost 8.2 Negative buck-boost 9 Package information 9.1 HTSSOP16 package information 10 Ordering information Revision history
VBIAS 1 16 GND VIN 2 15 BOOT VIN 3 14 LX VCC 4 EXPOSED 13 LX PAD TO EN 5 SGND 12 PGOOD SS 6 11 ILIM SYNCH 7 10 FSW COMP 8 9 FB
3.2 Pin description Table 1. Pin description # Pin Description
Auxiliary input that can be used to supply part of the analog circuitry to increase the efficiency at light load. 1 VBIAS Typically connected to the regulated output voltage or to an external voltage rail higher than 3 V. Connect to GND if not used or bypass with a 1 µF ceramic capacitor if supplied by the output voltage or by an auxiliary rail. 2 VIN DC input voltage 3 VIN DC input voltage 4 VCC Filtered DC input voltage to the internal circuitry. Bypass to GND with a 1 µF ceramic capacitor. 5 EN Active high enable pin. Connect to VCC pin if not used. Soft-start programming pin. An internal current generator (5 µA typ.) charges the external capacitor to 6 SS implement the soft start. 7 SYNCH Master / slave synchronization 8 COMP Output of the error amplifier. The designed compensation network is connected at this pin. 9 FB Inverting input of the error amplifier. 10 FSW A pull down resistor to GND selects the switching frequency. 11 ILIM A pull down resistor to GND selects the peak current limitation. The PGOOD open collector output is driven low when the output voltage, sensed on the FB pin, is out of 12 PGOOD regulation. 13 LX Switching node 14 LX Switching node Connect an external capacitor (100 nF typ.) between BOOT and LX pins. The gate charge required to drive the 15 BOOT internal n-DMOS is recovered by an internal regulator during the off-time.
DS12928
-
Rev 1 page 4/37
Document Outline Cover image Product status link / summary Features Applications Description 1 Application schematic 2 Block diagram 3 Pin settings 3.1 Pin connection 3.2 Pin description 3.3 Maximum ratings 3.4 Thermal data 3.5 ESD protection 4 Electrical characteristics 5 Functional description 5.1 Oscillator and synchronization 5.2 Soft-start 5.3 Error amplifier and light-load management 5.4 Low VIN operation 5.5 Overcurrent protection 5.6 Overtemperature protection 6 Application information 6.1 Input capacitor selection 6.2 Output capacitor selection 6.3 Inductor selection 6.4 Compensation network 6.4.1 Type II compensation network 6.4.2 Type III compensation network 6.5 Thermal considerations 6.6 Layout considerations 7 Demonstration board 8 Application ideas 8.1 Positive buck-boost 8.2 Negative buck-boost 9 Package information 9.1 HTSSOP16 package information 10 Ordering information Revision history
