Datasheet AD4003-KGD (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 18-Bit, 2 MSPS, Easy Drive, Differential SAR ADC |
| Pages / Page | 9 / 6 — AD4003-KGD. Known Good Die. Table 3. Register Read/Write Timing … |
| File Format / Size | PDF / 240 Kb |
| Document Language | English |
AD4003-KGD. Known Good Die. Table 3. Register Read/Write Timing Parameter. Symbol. Min. Typ. Max. Unit. Y% VIO1. X% VIO1. tDELAY. V 2. VIL
Model Line for this Datasheet
Text Version of Document
AD4003-KGD Known Good Die Table 3. Register Read/Write Timing Parameter Symbol Min Typ Max Unit
READ/WRITE OPERATION CNV Pulse Width1 tCNVH 10 ns SCK Period tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns READ OPERATION CNV Low to SDO D17 MSB Valid Delay tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV Rising Edge to SDO High Impedance tDIS 20 ns CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 190 ns WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge tSSDISCK
2 ns SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns 1 For turbo mode, tCNVH must match the tQUIET1 minimum.
Y% VIO1 X% VIO1 tDELAY tDELAY V 2 V 2 IH IH 2 V 2 VIL IL 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
002
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1.
16525- Figure 2. Voltage Levels for Timing
Table 4. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit
THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 2 MSPS 3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS 3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS 3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.44 MSPS Rev. 0 | Page 6 of 9 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide
READ/WRITE OPERATION CNV Pulse Width1 tCNVH 10 ns SCK Period tSCK VIO > 2.7 V 9.8 ns VIO > 1.7 V 12.3 ns SCK Low Time tSCKL 3 ns SCK High Time tSCKH 3 ns READ OPERATION CNV Low to SDO D17 MSB Valid Delay tEN VIO > 2.7 V 10 ns VIO > 1.7 V 13 ns SCK Falling Edge to Data Remains Valid tHSDO 1.5 ns SCK Falling Edge to Data Valid Delay tDSDO VIO > 2.7 V 7.5 ns VIO > 1.7 V 10.5 ns CNV Rising Edge to SDO High Impedance tDIS 20 ns CNV RISING EDGE TO FIRST SCK RISING EDGE DELAY tQUIET1 190 ns WRITE OPERATION SDI Valid Setup Time from SCK Rising Edge tSSDISCK
2 ns SDI Valid Hold Time from SCK Rising Edge tHSDISCK 2 ns CNV Rising Edge to SCK Edge Hold Time tHCNVSCK 0 ns CNV Falling Edge to SCK Active Edge Setup Time tSCNVSCK 6 ns 1 For turbo mode, tCNVH must match the tQUIET1 minimum.
Y% VIO1 X% VIO1 tDELAY tDELAY V 2 V 2 IH IH 2 V 2 VIL IL 1FOR VIO ≤ 2.7V, X = 80, AND Y = 20; FOR VIO > 2.7V, X = 70, AND Y = 30.
002
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS SPECIFICATIONS IN TABLE 1.
16525- Figure 2. Voltage Levels for Timing
Table 4. Achievable Throughput for Different Modes of Operation Parameter Test Conditions/Comments Min Typ Max Unit
THROUGHPUT, CS MODE 3-Wire and 4-Wire Turbo Mode fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 2 MSPS 3-Wire and 4-Wire Turbo Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 2 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.78 MSPS 3-Wire and 4-Wire Mode fSCK = 100 MHz, VIO ≥ 2.7 V 1.75 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.62 MSPS 3-Wire and 4-Wire Mode and Six Status Bits fSCK = 100 MHz, VIO ≥ 2.7 V 1.59 MSPS fSCK = 80 MHz, VIO < 2.7 V 1.44 MSPS Rev. 0 | Page 6 of 9 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide
