Datasheet ADRF6518 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | 1.1 GHz Variable Gain Amplifiers and Baseband Programmable Filters |
| Pages / Page | 39 / 2 — ADRF6518. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 12/2017—Rev. 0 … |
| Revision | A |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
ADRF6518. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY 12/2017—Rev. 0 to Rev. A. 6/2013—Revision 0: Initial Version
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ADRF6518 Data Sheet TABLE OF CONTENTS
Features .. 1 Key Parameters for Quadrature-Based Receivers .. 25 Applications ... 1 Applications Information .. 26 Functional Block Diagram .. 1 Basic Connections .. 26 General Description ... 1 Supply Decoupling ... 26 Revision History ... 2 Input Signal Path .. 26 Specifications ... 3 Output Signal Path ... 26 Timing Diagrams .. 5 DC Offset Compensation Loop Enabled .. 26 Absolute Maximum Ratings .. 6 Common-Mode Bypassing ... 27 ESD Caution .. 6 Serial Port Connections ... 27 Pin Configuration and Function Descriptions ... 7 Enable/Disable Function ... 27 Typical Performance Characteristics ... 8 Gain Pin Decoupling ... 27 Filter Mode .. 8 Peak Detector Connections .. 27 Bypass Mode ... 16 Error Vector Magnitude (EVM) Performance ... 27 Mixed Power and Filter Modes... 18 EVM Test Setup .. 27 Characterization ... 19 EVM Measurement .. 27 Noise Figure Calculation ... 19 EVM System Measurement ... 29 Register Map and Codes .. 20 Effect of Filter BW on EVM .. 31 Theory of Operation .. 21 Pull-Down Resistors for Disable Function ... 31 Input VGAs ... 21 Instability at High Gain in Filter Bypass Mode .. 31 Peak Detector .. 22 Instability at Low Filter Corners and Low Power Mode ... 32 Programmable Filters ... 22 Peak Detector Bandwidth And Slew Rate ... 32 Variable Gain Amplifiers (VGAs) .. 23 Linear Operation of the ADRF6518 .. 32 Output Buffers/ADC Drivers ... 23 Evaluation Board .. 33 DC Offset Compensation Loop .. 23 Evaluation Board Control Software ... 33 Programming the ADRF6518 ... 23 Schematics and Artwork ... 34 Noise Characteristics ... 24 Outline Dimensions ... 39 Distortion Characteristics ... 24 Ordering Guide .. 39 Maximizing the Dynamic Range .. 25
REVISION HISTORY 12/2017—Rev. 0 to Rev. A
Changes to Figure 56.. 16 Changed 1100 MHz to 1.1 GHz .. Throughout Changes to Figure 69 and Figure 69 Caption ... 22 Change to Product Title ... 1 Changes to Figure 72.. 26 Changes to Figure 1 .. 1 Changes to Figure 73 and Figure 74 .. 28 Changes to Table 1 .. 3 Added Figure 86 and Figure 87; Renumbered Sequentially .. 32 Changes to Figure 3 .. 5 Added Instability at Low Filter Corners and Low Power Mode Changes to Figure 12 .. 9 Section, and Peak Detector Bandwidth and Slew Rate Section .. . 32 Changes to Figure 20 .. 10 Changes to Figure 88 ... 32 Reorganized Typical Performance Characteristics Section; Changes to Figure 89.. 33 Renumbered Sequential y .. 10
Changes to Figure 49 Caption, Figure 51 Caption, and Figure 52
6/2013—Revision 0: Initial Version
Caption ... 15 Rev. A | Page 2 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
ADRF6518 Data Sheet TABLE OF CONTENTS
Features .. 1 Key Parameters for Quadrature-Based Receivers .. 25 Applications ... 1 Applications Information .. 26 Functional Block Diagram .. 1 Basic Connections .. 26 General Description ... 1 Supply Decoupling ... 26 Revision History ... 2 Input Signal Path .. 26 Specifications ... 3 Output Signal Path ... 26 Timing Diagrams .. 5 DC Offset Compensation Loop Enabled .. 26 Absolute Maximum Ratings .. 6 Common-Mode Bypassing ... 27 ESD Caution .. 6 Serial Port Connections ... 27 Pin Configuration and Function Descriptions ... 7 Enable/Disable Function ... 27 Typical Performance Characteristics ... 8 Gain Pin Decoupling ... 27 Filter Mode .. 8 Peak Detector Connections .. 27 Bypass Mode ... 16 Error Vector Magnitude (EVM) Performance ... 27 Mixed Power and Filter Modes... 18 EVM Test Setup .. 27 Characterization ... 19 EVM Measurement .. 27 Noise Figure Calculation ... 19 EVM System Measurement ... 29 Register Map and Codes .. 20 Effect of Filter BW on EVM .. 31 Theory of Operation .. 21 Pull-Down Resistors for Disable Function ... 31 Input VGAs ... 21 Instability at High Gain in Filter Bypass Mode .. 31 Peak Detector .. 22 Instability at Low Filter Corners and Low Power Mode ... 32 Programmable Filters ... 22 Peak Detector Bandwidth And Slew Rate ... 32 Variable Gain Amplifiers (VGAs) .. 23 Linear Operation of the ADRF6518 .. 32 Output Buffers/ADC Drivers ... 23 Evaluation Board .. 33 DC Offset Compensation Loop .. 23 Evaluation Board Control Software ... 33 Programming the ADRF6518 ... 23 Schematics and Artwork ... 34 Noise Characteristics ... 24 Outline Dimensions ... 39 Distortion Characteristics ... 24 Ordering Guide .. 39 Maximizing the Dynamic Range .. 25
REVISION HISTORY 12/2017—Rev. 0 to Rev. A
Changes to Figure 56.. 16 Changed 1100 MHz to 1.1 GHz .. Throughout Changes to Figure 69 and Figure 69 Caption ... 22 Change to Product Title ... 1 Changes to Figure 72.. 26 Changes to Figure 1 .. 1 Changes to Figure 73 and Figure 74 .. 28 Changes to Table 1 .. 3 Added Figure 86 and Figure 87; Renumbered Sequentially .. 32 Changes to Figure 3 .. 5 Added Instability at Low Filter Corners and Low Power Mode Changes to Figure 12 .. 9 Section, and Peak Detector Bandwidth and Slew Rate Section .. . 32 Changes to Figure 20 .. 10 Changes to Figure 88 ... 32 Reorganized Typical Performance Characteristics Section; Changes to Figure 89.. 33 Renumbered Sequential y .. 10
Changes to Figure 49 Caption, Figure 51 Caption, and Figure 52
6/2013—Revision 0: Initial Version
Caption ... 15 Rev. A | Page 2 of 39 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS FILTER MODE BYPASS MODE MIXED POWER AND FILTER MODES CHARACTERIZATION NOISE FIGURE CALCULATION REGISTER MAP AND CODES THEORY OF OPERATION INPUT VGAs Driving ADRF6518 Single-Ended PEAK DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6518 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED COMMON-MODE BYPASSING SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING PEAK DETECTOR CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM TEST SETUP EVM MEASUREMENT EVM SYSTEM MEASUREMENT EFFECT OF FILTER BW ON EVM PULL-DOWN RESISTORS FOR DISABLE FUNCTION INSTABILITY AT HIGH GAIN IN FILTER BYPASS MODE INSTABILITY AT LOW FILTER CORNERS AND LOW POWER MODE PEAK DETECTOR BANDWIDTH AND SLEW RATE LINEAR OPERATION OF THE ADRF6518 EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK OUTLINE DIMENSIONS ORDERING GUIDE
