Datasheet ADRF6510 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 30 MHz Dual Programmable Filters and Variable Gain Amplifiers |
| Pages / Page | 32 / 5 — Data Sheet. ADRF6510. TIMING DIAGRAMS. CLK. tLH. tLS. tDS. tDH. DATA. … |
| Revision | B |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
Data Sheet. ADRF6510. TIMING DIAGRAMS. CLK. tLH. tLS. tDS. tDH. DATA. WRITE BIT. LSB. LSB + 1. MSB – 2. MSB – 1. MSB -. MSB 2. NOTES
Model Line for this Datasheet
Text Version of Document
Data Sheet ADRF6510 TIMING DIAGRAMS t t CLK PW CLK tLH tLS LE tDS tDH DATA WRITE BIT LSB LSB + 1 MSB – 2 MSB – 1 MSB - MSB 2 NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY
003
WORD REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE CORNER FREQUENCY WORD BIT IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
09002- Figure 2. Write Mode Timing Diagram
t t CLK PW tD CLK tLS LE tDS tDH DATA READ BIT DC DC DC DC DC SDO LSB LSB + 1 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY WORD
004
REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE CORNER FREQUENCY WORD BIT IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK.
09002- Figure 3. Read Mode Timing Diagram Rev. B | Page 5 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE
003
WORD REGISTER. FOR A WRITE OPERATION, THE FIRST BIT SHOULD BE A LOGIC 1. THE CORNER FREQUENCY WORD BIT IS THEN REGISTERED INTO THE DATA PIN ON CONSECUTIVE RISING EDGES OF THE CLOCK.
09002- Figure 2. Write Mode Timing Diagram
t t CLK PW tD CLK tLS LE tDS tDH DATA READ BIT DC DC DC DC DC SDO LSB LSB + 1 MSB – 2 MSB – 1 MSB NOTES 1. THE FIRST DATA BIT DETERMINES WHETHER THE PART IS WRITING TO OR READING FROM THE INTERNAL CORNER FREQUENCY WORD
004
REGISTER. FOR A READ OPERATION, THE FIRST BIT SHOULD BE A LOGIC 0. THE CORNER FREQUENCY WORD BIT IS THEN UPDATED AT THE SDO PIN ON CONSECUTIVE FALLING EDGES OF THE CLOCK.
09002- Figure 3. Read Mode Timing Diagram Rev. B | Page 5 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE
