Datasheet HMC681ALP5E (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 0.5 dB LSB GaAs MMIC 6-BIT Digital Variable Gain Amplifier with Serial Control, DC - 1 GHz |
| Pages / Page | 11 / 6 — HMC681ALP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN. AMPLIFIER … |
| File Format / Size | PDF / 825 Kb |
| Document Language | English |
HMC681ALP5E. 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN. AMPLIFIER w/ SERIAL CONTROL, DC - 1 GHz
Model Line for this Datasheet
Text Version of Document
HMC681ALP5E
v00.0113
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER w/ SERIAL CONTROL, DC - 1 GHz Serial Control Interface
The HMC681ALP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, T 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data M transition during output loading. For all modes of operations, gain will remain constant while LE is kept low. L - S ITA IG S - D R IE LIF P M IN A A LE G B IA R
Truth Table
A V Parameter Typ. Serial Word Relative Gain Min. serial period, t 100 ns B5 B4 B3 B2 B1 B0 SCK Setting 16 dB 8dB 4 dB 2 dB 1 dB 0.5 dB Control set-up time, t 20 ns CS Reference Control hold-time, t 20 ns High High High High High High CH 0 dB LE setup-time, t 10 ns LN High High High High High Low -0.5 dB Min. LE pulse width, t 10 ns LEW High High High High Low High -1 dB Min LE pulse spacing, t 630 ns LES High High High Low High High -2 dB Serial clock hold-time from LE, t 10 ns CKN High High Low High High High -4 dB Hold Time, t 0 ns PH. High Low High High High High -8 dB Latch Enable Minimum Width, t 10 ns LEN Low High High High High High -16 dB Setup Time, t 2 ns PS Low Low Low Low Low Low -31.5 dB Any combination of the above states will provide a relative gain setting approximately equal to the sum of the bits selected. I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com
6
Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 o pplic r a atio pp n S s u @ p h por ittti : Pte. ho c n o e m : 1-800-ANALOG-D
v00.0113
0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER w/ SERIAL CONTROL, DC - 1 GHz Serial Control Interface
The HMC681ALP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, T 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data M transition during output loading. For all modes of operations, gain will remain constant while LE is kept low. L - S ITA IG S - D R IE LIF P M IN A A LE G B IA R
Truth Table
A V Parameter Typ. Serial Word Relative Gain Min. serial period, t 100 ns B5 B4 B3 B2 B1 B0 SCK Setting 16 dB 8dB 4 dB 2 dB 1 dB 0.5 dB Control set-up time, t 20 ns CS Reference Control hold-time, t 20 ns High High High High High High CH 0 dB LE setup-time, t 10 ns LN High High High High High Low -0.5 dB Min. LE pulse width, t 10 ns LEW High High High High Low High -1 dB Min LE pulse spacing, t 630 ns LES High High High Low High High -2 dB Serial clock hold-time from LE, t 10 ns CKN High High Low High High High -4 dB Hold Time, t 0 ns PH. High Low High High High High -8 dB Latch Enable Minimum Width, t 10 ns LEN Low High High High High High -16 dB Setup Time, t 2 ns PS Low Low Low Low Low Low -31.5 dB Any combination of the above states will provide a relative gain setting approximately equal to the sum of the bits selected. I F nf o or r p mati r o in cfe ur , d nish e e l d iv b e y r A y a nalo n g d t Devi o p ces i la s c bele o ieve rd d t e o rbs e : H acc iutrtatite e M and ic reli rao bl w e. a H v o e C wever o , nrp o For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other oration, 2 Elizabeth Drive, Chelmsford, MA 01824 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 978-250-3343 Fax: 978-250-3373 O rights of third parties that may result from its use. Specifications subject to change without notice. No rd Phoe n r O e: 7 n- 81-li 3 n 2 e a 9-4 t w 70 ww 0 • O . rdh e itt r o it nle i . n co e a m license is granted by implication or otherwise under any patent or patent rights of Analog Devices. t www.analog.com
6
Application Support: Phon Trademarks and registered trademarks are the property of their respective owners. e: 978-250-334 A 3 o pplic r a atio pp n S s u @ p h por ittti : Pte. ho c n o e m : 1-800-ANALOG-D
