Datasheet 5X2503 (IDT) - 3
| Manufacturer | IDT |
| Description | MicroClock Programmable Clock Generator with Embedded Crystal |
| Pages / Page | 30 / 3 — Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN … |
| Revision | 20171218 |
| File Format / Size | PDF / 418 Kb |
| Document Language | English |
Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package. 2.5 × 2.5 mm 12-DFN
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Text Version of Document
5X2503 Datasheet
Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package
SDA_DFC0/OE2 1 12 VSS SEL_DFC/SCL_DFC1/OE3 2 11 OUT3 VSS 3 10 VDDOUT2 VSS 4 9 OUT2 VDD1_8 5 8 OE1 VDDOUT1 6 7 OUT1
2.5 × 2.5 mm 12-DFN Pin Descriptions Table 1. Pin Descriptions Number Name Type Description
1 SDA_DFC0/OE2 I/O I2C data pin; can be DFC0 function by OTP programming or selected by SEL_DFC at power-on default. Output enable pin for OUT2. 2 SEL_DFC/SCL_DFC1/OE3 Input I2C clock pin; can be DFC1 function by OTP programming selected by SEL_DFC at power-on default. Output enable pin for OUT3. 3 VSS Power Ground pin. 4 VSS Power Ground pin. 5 VDD1_8 Power 1.8V power rail. 6 VDDOUT1 Power 1.2V / 1.8V output clock power supply pin; supports OUT1. 7 OUT1 Output 1.2V / 1.8V LVCMOS clock output. 8 OE1 Input Output enable control 1. 9 OUT2 Output 1.8V LVCMOS clock output. 10 VDDOUT2 Power 1.8V output clock power supply pin; supports OUT2/3. 11 OUT3 Output 1.8V LVCMOS clock output. 12 VSS Power Ground pin. – EPAD GND Connect to ground pad.
Device Feature and Function DFC – Dynamic Frequency Control
▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2. ▪ ORT (overshoot reduction) function will be applied automatical y during the VCO frequency change. ▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection. ©2017 Integrated Device Technology, Inc 3 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History
Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package
SDA_DFC0/OE2 1 12 VSS SEL_DFC/SCL_DFC1/OE3 2 11 OUT3 VSS 3 10 VDDOUT2 VSS 4 9 OUT2 VDD1_8 5 8 OE1 VDDOUT1 6 7 OUT1
2.5 × 2.5 mm 12-DFN Pin Descriptions Table 1. Pin Descriptions Number Name Type Description
1 SDA_DFC0/OE2 I/O I2C data pin; can be DFC0 function by OTP programming or selected by SEL_DFC at power-on default. Output enable pin for OUT2. 2 SEL_DFC/SCL_DFC1/OE3 Input I2C clock pin; can be DFC1 function by OTP programming selected by SEL_DFC at power-on default. Output enable pin for OUT3. 3 VSS Power Ground pin. 4 VSS Power Ground pin. 5 VDD1_8 Power 1.8V power rail. 6 VDDOUT1 Power 1.2V / 1.8V output clock power supply pin; supports OUT1. 7 OUT1 Output 1.2V / 1.8V LVCMOS clock output. 8 OE1 Input Output enable control 1. 9 OUT2 Output 1.8V LVCMOS clock output. 10 VDDOUT2 Power 1.8V output clock power supply pin; supports OUT2/3. 11 OUT3 Output 1.8V LVCMOS clock output. 12 VSS Power Ground pin. – EPAD GND Connect to ground pad.
Device Feature and Function DFC – Dynamic Frequency Control
▪ OTP programmable–4 different feedback fractional dividers (4 VCO frequencies) that apply to PLL2. ▪ ORT (overshoot reduction) function will be applied automatical y during the VCO frequency change. ▪ Smooth frequency incremental or decremental from current VCO to targeted VCO base on DFC hardware pins selection. ©2017 Integrated Device Technology, Inc 3 December 18, 2017 Document Outline Description Typical Applications Features Output Features Key Specifications Block Diagram Power Group Output Source Selection Register Setting Tables Pin Assignments Figure 1. Pin Assignments for 2.5 × 2.5 mm 12-DFN Package Pin Descriptions Table 1. Pin Descriptions Device Feature and Function DFC – Dynamic Frequency Control Figure 2. DFC Function Block Diagram Table 2. DFC Function Priority DFC Function Programming PPS – Proactive Power Saving Function Figure 3. PPS Function Block Diagram Figure 4. PPS Assertion/Deassertion Timing Chart PPS Function Programming Input Pin Function Table 3. OE1 Pin Function Table Table 4. SDA/SCL Function Selection Spread Spectrum ORT – VCO Overshoot Reduction Technology PLL Features and Descriptions Table 5. Output Divider 1 Table 6. Output Divider 2, 3, and 5 Table 7. Output Divider 4 Output Clock Test Conditions Figure 5. LVCMOS Output Clock Test Condition Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Recommended Operating Conditions Table 9. Recommended Operating Conditions Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance (TA = +25 °C) Table 10. Input Capacitance, LVCMOS Output Impedance, and Internal Pull-down Resistance Integrated Crystal Characteristics Table 11. Crystal Characteristics DC Electrical Characteristics Table 12. DC Electrical Characteristics 1,2 Electrical Characteristics–Input Parameters Table 13. Electrical Characteristics–Input Parameters 1 DC Electrical Characteristics for 1.8V LVCMOS Table 14. DC Electrical Characteristics – 1.8V LVCMOS AC Electrical Characteristics Table 15. AC Timing Electrical Characteristics – 32.768kHz Table 16. AC Timing Electrical Characteristics – 1.8V Table 17. AC Timing Electrical Characteristics, 1.2V / 1.8V I2C Bus DC Characteristics Table 18. I2C Bus DC Characteristics Table 19. I2C Bus AC Characteristics Spread Spectrum Generation Specifications Table 20. Spread Spectrum Generation Specifications General SMBus Serial Interface Information Package Outline Drawings Figure 6. NDG12 Package Drawing – page 1 Figure 7. NDG12 Package Drawing – page 2 Ordering Information Marking Diagram Revision History
