Datasheet BC3602 (Holtek) - 8
| Manufacturer | Holtek |
| Description | Sub-1GHz Low RX Current FSK/GFSK RF Transceiver |
| Pages / Page | 61 / 8 — BC3602. Bit. Addr. Name. • CFG1: Configuration Control Register 1. … |
| File Format / Size | PDF / 1.3 Mb |
| Document Language | English |
BC3602. Bit. Addr. Name. • CFG1: Configuration Control Register 1. AGC_EN. RXCON_EN. DIR_EN. BANK[1:0]
Model Line for this Datasheet
Text Version of Document
BC3602 Bit Addr. Name 7 6 5 4 3 2 1 0
18h DM2 PREAMBLE_ PREAMBLE_ CFO_EN1 CFO_EN0 SDR[5:0] 19h DM3 CSF_SW_EN FD_MOD[6:0] 1Ah DM4 THOLD[3:0] CFO_ PRE_ DSEL — PH_DIFF_ MOD CSF_EN 1Bh DM5 FD_HOLD[7:0] 1Eh DM8 M_RATIO[7:0] Note: Addresses 05h, 1Ch, 1Dh and 1Fh, which are not listed in this table are reserved for future use, it is suggested not to change their initial values by any methods. The reset value shown in the following register description tables means the software reset results of strobe command.
• CFG1: Configuration Control Register 1 Bit 7 6 5 4 3 2 1 0
Name — AGC_EN RXCON_EN DIR_EN — — BANK[1:0] R/W — R/W R/W R/W — — R/W Reset 0 0 0 0 0 0 0 0 Bit 7 Reserved, must be “0” Bit 6
AGC_EN
: AGC enable 0: Disable 1: Enable Bit 5
RXCON_EN
: RX continue mode enable 0: Disable 1: Enable Note that this bit only affects normal RX mode and ATR RX mode without ARK function. Bit 4
DIR_EN
: Direct mode enable 0: TX/RX data from packet handling hardware 1: TX/RX data from/to external MCU directly Bit 3~2 Reserved, must be “00” Bit 1~0
BANK[1:0]
: Control register bank selection 00: Bank 0 01: Bank 1 10: Bank 2 11: Reserved This selection can be set by both the Set Register Bank command and Control Register command. Rev. 1.00 8 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
18h DM2 PREAMBLE_ PREAMBLE_ CFO_EN1 CFO_EN0 SDR[5:0] 19h DM3 CSF_SW_EN FD_MOD[6:0] 1Ah DM4 THOLD[3:0] CFO_ PRE_ DSEL — PH_DIFF_ MOD CSF_EN 1Bh DM5 FD_HOLD[7:0] 1Eh DM8 M_RATIO[7:0] Note: Addresses 05h, 1Ch, 1Dh and 1Fh, which are not listed in this table are reserved for future use, it is suggested not to change their initial values by any methods. The reset value shown in the following register description tables means the software reset results of strobe command.
• CFG1: Configuration Control Register 1 Bit 7 6 5 4 3 2 1 0
Name — AGC_EN RXCON_EN DIR_EN — — BANK[1:0] R/W — R/W R/W R/W — — R/W Reset 0 0 0 0 0 0 0 0 Bit 7 Reserved, must be “0” Bit 6
AGC_EN
: AGC enable 0: Disable 1: Enable Bit 5
RXCON_EN
: RX continue mode enable 0: Disable 1: Enable Note that this bit only affects normal RX mode and ATR RX mode without ARK function. Bit 4
DIR_EN
: Direct mode enable 0: TX/RX data from packet handling hardware 1: TX/RX data from/to external MCU directly Bit 3~2 Reserved, must be “00” Bit 1~0
BANK[1:0]
: Control register bank selection 00: Bank 0 01: Bank 1 10: Bank 2 11: Reserved This selection can be set by both the Set Register Bank command and Control Register command. Rev. 1.00 8 July 29, 2019 Document Outline Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics A.C. Characteristics Memory Mapping Control Register Access SFR Mapping and Bit Definition Common Area Control Register Bank 0 Control Registers Bank 1 Control Registers Bank 2 Control Registers Special Function Description Sub-1GHz RF Transceiver Serial Interface System Clock Frequency Synthesizer Modulator State Machine Calibration AGC & RSSI Packet Handler FIFO Operation Modes Receiving Packet Judgement Continuous RX Mode ARK Mode: Auto-Resend and Auto-Ack ATR Mode: Auto-Transmit-Receive Message Flowchart Examples Abbreviation Application Circuits Package Information SAW Type 24-pin QFN (3mm×3mm×0.55mm) Outline Dimensions
