Datasheet AP3917D (Diodes) - 9
| Manufacturer | Diodes |
| Description | Universal AC High Voltage Step Down Power Switcher |
| Pages / Page | 12 / 9 — AP3917D. Performance Characteristics. Open-Loop Detection. Overshoot … |
| File Format / Size | PDF / 587 Kb |
| Document Language | English |
AP3917D. Performance Characteristics. Open-Loop Detection. Overshoot Improvement. T C U. E N. Leading-Edge Blanking. www.diodes.com
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AP3917D Performance Characteristics
(continued)
Open-Loop Detection
When the FB voltage drops below open-loop detection threshold voltage VOLD (60mV), the AP3917D stops working and begins a restart cycle. The open-loop detection is blanked for 64 switching cycles during startup process.
Overshoot Improvement
In general, there is no capacitor between FB pin and S pin. But in some cases where strict overshoot is required, we recommend a ceramic capacitor C6 (390pF to 1nF) in Figure 5.
T C U
R1 D2
D
C3
O
C2
R
C6 R2
P
L2
W
BP S VO+
E N
FB S NC Drain NC AP3917D Figure 5. Overshoot Improvement
Leading-Edge Blanking
A narrow spike on the leading edge of the current waveform can usually be observed when the power MOSFET is turned on. Normally, the leading-edge blanking time tLEB1 is built in to prevent the false-triggering caused by the turn-on spike. But in the case of short circuit, the leading- edge blanking time is tLEB2. During this period, the current limit comparator is disabled, and the gate driver cannot be switched off. AP3917D 9 of 12 June 2019 Document number: DS41540 Rev. 4 - 2
www.diodes.com
© Diodes Incorporated
(continued)
Open-Loop Detection
When the FB voltage drops below open-loop detection threshold voltage VOLD (60mV), the AP3917D stops working and begins a restart cycle. The open-loop detection is blanked for 64 switching cycles during startup process.
Overshoot Improvement
In general, there is no capacitor between FB pin and S pin. But in some cases where strict overshoot is required, we recommend a ceramic capacitor C6 (390pF to 1nF) in Figure 5.
T C U
R1 D2
D
C3
O
C2
R
C6 R2
P
L2
W
BP S VO+
E N
FB S NC Drain NC AP3917D Figure 5. Overshoot Improvement
Leading-Edge Blanking
A narrow spike on the leading edge of the current waveform can usually be observed when the power MOSFET is turned on. Normally, the leading-edge blanking time tLEB1 is built in to prevent the false-triggering caused by the turn-on spike. But in the case of short circuit, the leading- edge blanking time is tLEB2. During this period, the current limit comparator is disabled, and the gate driver cannot be switched off. AP3917D 9 of 12 June 2019 Document number: DS41540 Rev. 4 - 2
www.diodes.com
© Diodes Incorporated
