Datasheet ADP5071 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | 2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs |
| Pages / Page | 27 / 3 — Data Sheet. ADP5071. SPECIFICATIONS. Table 2. Parameter. Symbol. Min. … |
| Revision | E |
| File Format / Size | PDF / 1.0 Mb |
| Document Language | English |
Data Sheet. ADP5071. SPECIFICATIONS. Table 2. Parameter. Symbol. Min. Typ. Max. Unit. Test Conditions/Comments
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Data Sheet ADP5071 SPECIFICATIONS
PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, VPOS = 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.85 15 V PVIN1, PVIN2, PVINSYS QUIESCENT CURRENT Operating Quiescent Current PVIN1, PVIN2, PVINSYS (Total) IQ 3.5 4.0 mA No switching, EN1 = EN2 = high, PVIN1 = PVIN2 = PVINSYS = 5 V Shutdown Current ISHDN 5 10 µA No switching, EN1 = EN2 = low, PVIN1 = PVIN2 = PVINSYS = 5 V UVLO System UVLO Threshold PVINSYS Rising VUVLO_RISING 2.8 2.85 V Falling VUVLO_FALLING 2.5 2.55 V Hysteresis VHYS_1 0.25 V OSCILLATOR CIRCUIT Switching Frequency fSW 1.130 1.200 1.270 MHz SYNC/FREQ = low 2.240 2.400 2.560 MHz SYNC/FREQ = high (connect to VREG) SYNC/FREQ Input Input Clock Range fSYNC 1.000 2.600 MHz Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns Input Clock High Logic VH (SYNC) 1.3 V Input Clock Low Logic VL (SYNC) 0.4 V PRECISION ENABLING (EN1, EN2) High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve ISHDN Pull-Down Resistance REN 1.48 MΩ INTERNAL REGULATOR VREG Output Voltage VREG 4.25 V BOOST REGULATOR Feedback Voltage VFB1 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C −1.5 +1.5 % TJ = −40°C to +125°C Feedback Bias Current IFB1 0.1 µA Overvoltage Protection Threshold VOV1 0.86 V At FB1 pin Load Regulation ∆V 1 FB1/ILOAD1 0.0003 %/mA ILOAD1 = 5 mA to 150 mA Line Regulation ∆V 1 FB1/VPVIN1 0.002 %/V VPVIN1 = 2.85 V to 14.5 V, ILOAD1 = 50 mA Error Amplifier (EA) Transconductance gM1 270 300 330 µA/V Power FET On Resistance RDS (ON) BOOST 175 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) BOOST 39 V Input Disconnect Switch On Resistance RDS (ON) INBK 210 mΩ Current-Limit Threshold ILIM (BOOST) 2.0 2.2 2.4 A Minimum On Time 50 ns Minimum Off Time 25 ns Rev. E | Page 3 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide
Data Sheet ADP5071 SPECIFICATIONS
PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, VPOS = 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE VIN 2.85 15 V PVIN1, PVIN2, PVINSYS QUIESCENT CURRENT Operating Quiescent Current PVIN1, PVIN2, PVINSYS (Total) IQ 3.5 4.0 mA No switching, EN1 = EN2 = high, PVIN1 = PVIN2 = PVINSYS = 5 V Shutdown Current ISHDN 5 10 µA No switching, EN1 = EN2 = low, PVIN1 = PVIN2 = PVINSYS = 5 V UVLO System UVLO Threshold PVINSYS Rising VUVLO_RISING 2.8 2.85 V Falling VUVLO_FALLING 2.5 2.55 V Hysteresis VHYS_1 0.25 V OSCILLATOR CIRCUIT Switching Frequency fSW 1.130 1.200 1.270 MHz SYNC/FREQ = low 2.240 2.400 2.560 MHz SYNC/FREQ = high (connect to VREG) SYNC/FREQ Input Input Clock Range fSYNC 1.000 2.600 MHz Input Clock Minimum On Pulse Width tSYNC_MIN_ON 100 ns Input Clock Minimum Off Pulse Width tSYNC_MIN_OFF 100 ns Input Clock High Logic VH (SYNC) 1.3 V Input Clock Low Logic VL (SYNC) 0.4 V PRECISION ENABLING (EN1, EN2) High Level Threshold VTH_H 1.125 1.15 1.175 V Low Level Threshold VTH_L 1.025 1.05 1.075 V Shutdown Mode VTH_S 0.4 V Internal circuitry disabled to achieve ISHDN Pull-Down Resistance REN 1.48 MΩ INTERNAL REGULATOR VREG Output Voltage VREG 4.25 V BOOST REGULATOR Feedback Voltage VFB1 0.8 V Feedback Voltage Accuracy −0.5 +0.5 % TJ = 25°C −1.5 +1.5 % TJ = −40°C to +125°C Feedback Bias Current IFB1 0.1 µA Overvoltage Protection Threshold VOV1 0.86 V At FB1 pin Load Regulation ∆V 1 FB1/ILOAD1 0.0003 %/mA ILOAD1 = 5 mA to 150 mA Line Regulation ∆V 1 FB1/VPVIN1 0.002 %/V VPVIN1 = 2.85 V to 14.5 V, ILOAD1 = 50 mA Error Amplifier (EA) Transconductance gM1 270 300 330 µA/V Power FET On Resistance RDS (ON) BOOST 175 mΩ Power FET Maximum Drain Source Voltage VDS (MAX) BOOST 39 V Input Disconnect Switch On Resistance RDS (ON) INBK 210 mΩ Current-Limit Threshold ILIM (BOOST) 2.0 2.2 2.4 A Minimum On Time 50 ns Minimum Off Time 25 ns Rev. E | Page 3 of 27 Document Outline Features Applications Typical Application Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Theory of Operation PWM Mode PSM Mode Undervoltage Lockout (UVLO) Oscillator and Synchronization Internal Regulators Precision Enabling Soft Start Slew Rate Control Current-Limit Protection Overvoltage Protection Thermal Shutdown Start-Up Sequence Applications Information ADIsimPower Design Tool Component Selection Feedback Resistors Output Capacitors Input Capacitor VREG Capacitor VREF Capacitor Soft Start Resistor Diodes Inductor Selection for the Boost Regulator Inductor Selection for the Inverting Regulator Loop Compensation Boost Regulator Inverting Regulator Common Applications Super Low Noise With Optional LDOs SEPIC Step-Up/Step-Down Operation Layout Considerations Outline Dimensions Ordering Guide
