Datasheet LT7101 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 105V, 1A Low EMI Synchronous Step-Down Regulator with Fast Current Programming |
| Pages / Page | 38 / 10 — PIN FUNCTIONS PLLIN/MODE (Pin 12):. MON (Pin 17):. VPRG1, VPRG2 (Pins … |
| File Format / Size | PDF / 3.2 Mb |
| Document Language | English |
PIN FUNCTIONS PLLIN/MODE (Pin 12):. MON (Pin 17):. VPRG1, VPRG2 (Pins 18,19):. CLKOUT (Pin 13):. EXTVCC (Pin 20):
Model Line for this Datasheet
Text Version of Document
link to page 18 link to page 18 link to page 18 link to page 18 LT7101
PIN FUNCTIONS PLLIN/MODE (Pin 12):
External Synchronization Input pin allows a single resistor to SGND to be used to set the to Phase Detector and Burst Mode Control Input. When voltage. Float this pin to set the average output current to an external clock is applied to this pin, the phase-locked 1.11A and the peak current limit to 1.64A. loop will force the rising edge of the SW signal to be syn-
I
chronized with the rising edge of the external clock, and
MON (Pin 17):
Average Output Current Monitor. This pin generates a voltage between 0.4V and 1.3V that corre- the LT7101 operates in forced continuous mode. When sponds to an average output current between 0A and 1.11A. not synchronizing to an external clock, this input deter- mines how the LT7101 operates at light loads. Tie this
VPRG1, VPRG2 (Pins 18,19):
Output Voltage Programming pin to SGND or float to select Burst Mode operation or to Pins. These pins set the regulator to adjustable output INTVCC to force continuous inductor current operation. mode or to fixed output mode. Floating both pins allows Tie this pin to INTVCC through a 100k resistor to select the output to be programmed through the VFB pin using pulse-skipping operation. This pin sinks 10μA to SGND. external resistors, regulating VFB to the 1V reference. Tying one of these pins to SGND or INTV
CLKOUT (Pin 13):
Output clock signal available to syn- CC while the other is tied to SGND, INTV chronize additional regulators for parallel operation. The CC or floating programs the output to one of eight fixed output voltages. See Output Voltage rising edge of CLKOUT is 180° out of phase with respect Programming in the Applications Information section. to the rising edge of the SW pin. The output level swings from SGND to INTVCC.
EXTVCC (Pin 20):
External Power Input to an Internal LDO that Generates INTV
PGOOD (Pin 14):
Open-Drain Power Good Output. The CC. This LDO supplies INTVCC power from EXTV V CC, bypassing the internal LDO pow- FB pin is monitored to ensure that the output is in regu- ered from V lation. When the output is not in regulation, the PGOOD IN whenever EXTVCC is between 3.1V and 40V. If EXTV pin is pulled low. CC is not used, the regulator timeout feature must be disabled by tying a 75k resistor between SS
SS (Pin 15):
Soft-Start and Regulator Timeout Input. The and INTVCC. See INTVCC Regulations in the Applications voltage on the SS pin limits the regulated output voltage Information section. when the SS voltage is less than 1V. An internal 10μA
INTV
pull-up current source is connected to this pin. A capaci-
CC (Pin 21):
Output of the Internal LDO regulator. The driver and control circuits are powered from this voltage tor to ground at this pin sets the ramp time to final regu- source. Must be decoupled to PGND with a 1µF to 4.7μF lated output voltage. Leave this pin floating to use the ceramic capacitor. internal 1.2ms soft-start ramp. The SS pin also serves as a timeout to disable switching if the EXTVCC voltage
SW (Pins 24, 25, 26):
SW Node connection from the is too low. To disable the regulator timeout feature, tie a internal MOSFET power switches to the output inductor. 75k resistor between SS and INTVCC. See Soft-Start and
BOOST (Pin 27):
Bootstrapped Supply to the High Side LDO Regulator Timeout in the Applications Information Floating Gate Driver. Connect a 0.1µF ceramic capacitor section. between the BOOST and SW pins.
ICTRL (Pin 16):
Programs the Average Output Current in
V
Constant Current Mode. The voltage on this pin deter-
IN (Pins 30, 31, 32):
Power Input Supply. This is the power input to the integrated high side MOSFET switch as mines the maximum ITH voltage, which in turn sets the well as the input to the internal LDO that generates INTV average output current in constant-current mode. The CC voltage. Decouple this pin with a capacitor to PGND. peak current limit tracks 0.53A above the average current limit set point. Tie this pin to a voltage between 0.4V and
PGND/Exposed Pad (Pin 35, 36, 37):
Power Ground. 1.3V to program the average output current to a value Connect to power ground plane. The exposed pad must between 0A and 1.11A. An internal 20μA pull-up on this be connected to PCB ground for rated electrical and ther- mal performance. Rev. 0 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
PIN FUNCTIONS PLLIN/MODE (Pin 12):
External Synchronization Input pin allows a single resistor to SGND to be used to set the to Phase Detector and Burst Mode Control Input. When voltage. Float this pin to set the average output current to an external clock is applied to this pin, the phase-locked 1.11A and the peak current limit to 1.64A. loop will force the rising edge of the SW signal to be syn-
I
chronized with the rising edge of the external clock, and
MON (Pin 17):
Average Output Current Monitor. This pin generates a voltage between 0.4V and 1.3V that corre- the LT7101 operates in forced continuous mode. When sponds to an average output current between 0A and 1.11A. not synchronizing to an external clock, this input deter- mines how the LT7101 operates at light loads. Tie this
VPRG1, VPRG2 (Pins 18,19):
Output Voltage Programming pin to SGND or float to select Burst Mode operation or to Pins. These pins set the regulator to adjustable output INTVCC to force continuous inductor current operation. mode or to fixed output mode. Floating both pins allows Tie this pin to INTVCC through a 100k resistor to select the output to be programmed through the VFB pin using pulse-skipping operation. This pin sinks 10μA to SGND. external resistors, regulating VFB to the 1V reference. Tying one of these pins to SGND or INTV
CLKOUT (Pin 13):
Output clock signal available to syn- CC while the other is tied to SGND, INTV chronize additional regulators for parallel operation. The CC or floating programs the output to one of eight fixed output voltages. See Output Voltage rising edge of CLKOUT is 180° out of phase with respect Programming in the Applications Information section. to the rising edge of the SW pin. The output level swings from SGND to INTVCC.
EXTVCC (Pin 20):
External Power Input to an Internal LDO that Generates INTV
PGOOD (Pin 14):
Open-Drain Power Good Output. The CC. This LDO supplies INTVCC power from EXTV V CC, bypassing the internal LDO pow- FB pin is monitored to ensure that the output is in regu- ered from V lation. When the output is not in regulation, the PGOOD IN whenever EXTVCC is between 3.1V and 40V. If EXTV pin is pulled low. CC is not used, the regulator timeout feature must be disabled by tying a 75k resistor between SS
SS (Pin 15):
Soft-Start and Regulator Timeout Input. The and INTVCC. See INTVCC Regulations in the Applications voltage on the SS pin limits the regulated output voltage Information section. when the SS voltage is less than 1V. An internal 10μA
INTV
pull-up current source is connected to this pin. A capaci-
CC (Pin 21):
Output of the Internal LDO regulator. The driver and control circuits are powered from this voltage tor to ground at this pin sets the ramp time to final regu- source. Must be decoupled to PGND with a 1µF to 4.7μF lated output voltage. Leave this pin floating to use the ceramic capacitor. internal 1.2ms soft-start ramp. The SS pin also serves as a timeout to disable switching if the EXTVCC voltage
SW (Pins 24, 25, 26):
SW Node connection from the is too low. To disable the regulator timeout feature, tie a internal MOSFET power switches to the output inductor. 75k resistor between SS and INTVCC. See Soft-Start and
BOOST (Pin 27):
Bootstrapped Supply to the High Side LDO Regulator Timeout in the Applications Information Floating Gate Driver. Connect a 0.1µF ceramic capacitor section. between the BOOST and SW pins.
ICTRL (Pin 16):
Programs the Average Output Current in
V
Constant Current Mode. The voltage on this pin deter-
IN (Pins 30, 31, 32):
Power Input Supply. This is the power input to the integrated high side MOSFET switch as mines the maximum ITH voltage, which in turn sets the well as the input to the internal LDO that generates INTV average output current in constant-current mode. The CC voltage. Decouple this pin with a capacitor to PGND. peak current limit tracks 0.53A above the average current limit set point. Tie this pin to a voltage between 0.4V and
PGND/Exposed Pad (Pin 35, 36, 37):
Power Ground. 1.3V to program the average output current to a value Connect to power ground plane. The exposed pad must between 0A and 1.11A. An internal 20μA pull-up on this be connected to PCB ground for rated electrical and ther- mal performance. Rev. 0 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Functional Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
