Datasheet AD8304 (Analog Devices) - 2

AD8304–SPECIFICATIONS (VP = 5 V, VN = 0 V, TA = 25 C, unless otherwise noted.) Parameter Conditions Min1 Typ Max1 Unit
INPUT INTERFACE Pin 4, INPT; Pin 3 and Pin 5, VSUM Specified Current Range Flows toward INPT Pin 100 pA 10 mA Input Node Voltage Internally preset; may be altered 0.46 0.5 0.54 V Temperature Drift –40°C < TA < +85°C 0.02 mV/°C Input Guard Offset Voltage VIN – VSUM –20 +20 mV PHOTODIODE BIAS2 Established between Pin 6, VPDB, and Pin 4 Minimum Value IPD = 100 pA 70 100 mV Transresistance 200 mV/mA LOGARITHMIC OUTPUT Pin 8, VLOG Slope Laser-trimmed at 25°C 196 200 204 mV/dec 0°C < TA < 70°C 194 207 mV/dec Intercept Laser-trimmed at 25°C 60 100 140 pA 0°C < TA < 70°C 35 175 pA Law Conformance Error 10 nA < IPD < 1 mA, Peak Error 0.05 0.25 dB 1 nA < IPD < 1 mA, Peak Error 0.1 0.7 dB Maximum Output Voltage 1.6 V Minimum Output Voltage Limited by VN = 0 V 0.1 V Output Resistance Laser-trimmed at 25°C 4.95 5 5.05 kΩ REFERENCE OUTPUT Pin 7, VREF Voltage WRT Ground Laser-trimmed at 25°C 1.98 2 2.02 V –40°C < TA < +85°C 1.92 2.08 V Output Resistance 2 Ω OUTPUT BUFFER Pin 9, BFIN; Pin 13, BFNG; Pin 11, VOUT Input Offset Voltage –20 +20 mV Input Bias Current Flowing out of Pin 9 or Pin 13 0.4 µA Incremental Input Resistance 35 MΩ Output Range RL = 1 kΩ to ground VP – 0.1 V Output Resistance 0.5 Ω Wide-Band Noise3 IPD > 1 µA (see Typical Performance Characteristics) 1 µV/√Hz Small Signal Bandwidth3 IPD > 1 µA (see Typical Performance Characteristics) 10 MHz Slew Rate 0.2 V to 4.8 V output swing 15 V/µs POWER-DOWN INPUT Pin 2, PWDN Logic Level, HI State –40°C < TA < +85°C, 2.7 V < VP < 5.5 V 2 V Logic Level, LO State –40°C < TA < +85°C, 2.7 V < VP < 5.5 V 1 V POWER SUPPLY Pin 10 and Pin 12, VPS1 and VPS2; Pin 1, VNEG Positive Supply Voltage 3.0 5 5.5 V Quiescent Current 4.5 5.3 mA In Disabled State 60 µA Negative Supply Voltage4 |1VP –VN| < 8V 0 –5.5 V NOTES 1Minimum and maximum specified limits on parameters that are guaranteed but not tested are six sigma values. 2This bias is internally arranged to track the input voltage at

INPT; it is not specified relative to ground. 3Output Noise and Incremental Bandwidth are functions of Input Current; see Typical Performance Characteristics. 4Optional Specifications subject to change without notice. –2– REV. A Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS ORDERING GUIDE Typical Performance Characteristics BASIC CONCEPTS Optical Measurements Decibel Scaling GENERAL STRUCTURE Bandwidth and Noise Considerations Chip Enable USING THE AD8304 Slope and Intercept Adjustments Low Supply Slope and Intercept Adjustment Using the Adaptive Bias Changing the Voltage at the Summing Node Implementing Low-Pass Filters Operation in Comparator Modes Using a Negative Supply APPLICATIONS Summing Node at Ground and Voltage Inputs Providing Negative Outputs and Rescaling Inverting the Slope Programmable Level Comparator with Hysteresis Programmable Multidecade Current Source Characterization Setups and Methods Evaluation Board OUTLINE DIMENSIONS Revision History