Datasheet TPS7A02 (Texas Instruments) - 3
| Manufacturer | Texas Instruments |
| Description | Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient Response |
| Pages / Page | 23 / 3 — TPS7A02. www.ti.com. 5 Pin Configuration and Functions. DBV Package … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
TPS7A02. www.ti.com. 5 Pin Configuration and Functions. DBV Package (Preview). DQN Package. 5-Pin SOT-23. 1-mm × 1-mm X2SON-4
Model Line for this Datasheet
Text Version of Document
TPS7A02 www.ti.com
SBVS277 – JULY 2019
5 Pin Configuration and Functions DBV Package (Preview) DQN Package 5-Pin SOT-23 1-mm × 1-mm X2SON-4 Top View Top View
OUT 1 4 IN IN 1 5 OUT GND 2 EN 3 4 NC Thermal Pad GND 2 3 EN Not to scale Not to scale
Pin Functions: DQN, DBV PIN NAME DQN DBV(2) I/O(1) DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low EN 3 3 Input disables the device. If enable functionality is not required, this pin must be connected to IN. VEN must not exceed VIN.
TION
GND 2 2 — Ground pin. This pin must be connected to ground and the thermal pad. Input pin. A 0.1-µF or greater effective capacitance is required from IN to ground to minimize input impedance. For best transient response, use a 1-µF or larger ceramic IN 4 1 Input capacitor from IN to ground. Place the input capacitor as close to input of the device as possible. NC — 4 — No connect pin. This pin is not internally connected. Connect to ground or leave floating. Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor OUT 1 5 Output from OUT to ground. Place the output capacitor as close to output of the device as possible. Connect the thermal pad to a large-area ground plane. The thermal pad is internally Thermal pad –– — connect to ground.
ANCEINFORMA
(1) NC = No internal connection. (2) Preview package.
ADV
Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Switching Characteristics 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Excellent Transient Response 7.3.2 Active Discharge (P-Version Only) 7.3.3 Low IQ in Dropout 7.3.4 Smart Enable 7.3.5 Dropout Voltage 7.3.6 Foldback Current Limit 7.3.7 Undervoltage Lockout (UVLO) 7.3.8 Thermal Shutdown 7.4 Device Functional Modes 7.4.1 Device Functional Mode Comparison 7.4.2 Normal Operation 7.4.3 Dropout Operation 7.4.4 Disabled 8 Application and Implementation 8.1 Application Information 8.1.1 Recommended Capacitor Types 8.1.2 Input and Output Capacitor Requirements 8.1.3 Load Transient Response 8.1.4 Undervoltage Lockout (UVLO) Operation 8.1.5 Power Dissipation (PD) 8.1.5.1 Estimating Junction Temperature 8.1.5.2 Recommended Area for Continuous Operation 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Examples 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information
SBVS277 – JULY 2019
5 Pin Configuration and Functions DBV Package (Preview) DQN Package 5-Pin SOT-23 1-mm × 1-mm X2SON-4 Top View Top View
OUT 1 4 IN IN 1 5 OUT GND 2 EN 3 4 NC Thermal Pad GND 2 3 EN Not to scale Not to scale
Pin Functions: DQN, DBV PIN NAME DQN DBV(2) I/O(1) DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low EN 3 3 Input disables the device. If enable functionality is not required, this pin must be connected to IN. VEN must not exceed VIN.
TION
GND 2 2 — Ground pin. This pin must be connected to ground and the thermal pad. Input pin. A 0.1-µF or greater effective capacitance is required from IN to ground to minimize input impedance. For best transient response, use a 1-µF or larger ceramic IN 4 1 Input capacitor from IN to ground. Place the input capacitor as close to input of the device as possible. NC — 4 — No connect pin. This pin is not internally connected. Connect to ground or leave floating. Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor OUT 1 5 Output from OUT to ground. Place the output capacitor as close to output of the device as possible. Connect the thermal pad to a large-area ground plane. The thermal pad is internally Thermal pad –– — connect to ground.
ANCEINFORMA
(1) NC = No internal connection. (2) Preview package.
ADV
Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3 Document Outline 1 Features 2 Applications 3 Description Table of Contents 4 Revision History 5 Pin Configuration and Functions 6 Specifications 6.1 Absolute Maximum Ratings 6.2 ESD Ratings 6.3 Recommended Operating Conditions 6.4 Thermal Information 6.5 Electrical Characteristics 6.6 Switching Characteristics 6.7 Typical Characteristics 7 Detailed Description 7.1 Overview 7.2 Functional Block Diagram 7.3 Feature Description 7.3.1 Excellent Transient Response 7.3.2 Active Discharge (P-Version Only) 7.3.3 Low IQ in Dropout 7.3.4 Smart Enable 7.3.5 Dropout Voltage 7.3.6 Foldback Current Limit 7.3.7 Undervoltage Lockout (UVLO) 7.3.8 Thermal Shutdown 7.4 Device Functional Modes 7.4.1 Device Functional Mode Comparison 7.4.2 Normal Operation 7.4.3 Dropout Operation 7.4.4 Disabled 8 Application and Implementation 8.1 Application Information 8.1.1 Recommended Capacitor Types 8.1.2 Input and Output Capacitor Requirements 8.1.3 Load Transient Response 8.1.4 Undervoltage Lockout (UVLO) Operation 8.1.5 Power Dissipation (PD) 8.1.5.1 Estimating Junction Temperature 8.1.5.2 Recommended Area for Continuous Operation 8.2 Typical Application 8.2.1 Design Requirements 8.2.2 Detailed Design Procedure 9 Power Supply Recommendations 10 Layout 10.1 Layout Guidelines 10.2 Layout Examples 11 Device and Documentation Support 11.1 Device Support 11.1.1 Device Nomenclature 11.2 Receiving Notification of Documentation Updates 11.3 Community Resources 11.4 Trademarks 11.5 Electrostatic Discharge Caution 11.6 Glossary 12 Mechanical, Packaging, and Orderable Information
