Datasheet ATA663431, ATA663454 (Microchip) - 5

ManufacturerMicrochip
DescriptionLIN SBC including LIN Transceiver, Voltage Regulator, Window Watchdog and High-Side Switch
Pages / Page40 / 5 — ATA663431/54. FIGURE 1-3:. SWITCHING TO SLEEP MODE. Sleep Mode. Normal …
File Format / SizePDF / 1.1 Mb
Document LanguageEnglish

ATA663431/54. FIGURE 1-3:. SWITCHING TO SLEEP MODE. Sleep Mode. Normal Mode

ATA663431/54 FIGURE 1-3: SWITCHING TO SLEEP MODE Sleep Mode Normal Mode

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ATA663431/54
1.2.3 SLEEP MODE A falling edge at EN while TXD is low switches the IC to Sleep mode. The TXD signal has to be logic low during the mode select window.
FIGURE 1-3: SWITCHING TO SLEEP MODE Sleep Mode Normal Mode
EN Mode select window TXD td = 3.2μs NRES VCC Delay time sleep mode td_sleep = maximum 20μs LIN LIN switches directly to recessive mode In order to avoid any influence to the LIN pin while switching into Sleep mode, it is possible to switch the EN to low up to 3.2 μs earlier than the TXD. The best and easiest way is to generate two simultaneous falling edges at TXD and EN. The transmission path is disabled in Sleep mode. Supply current from VBAT is typically IVSsleep = 10 μA. The VCC regulator is switched off; NRES and RXD are low. The internal slave termination between the LIN and VS pins is disabled to minimize current consumption in case the LIN pin is short-circuited to GND. Only a weak pull-up current (typically 10 μA) between the LIN pin and VS pin is present. Sleep mode can be activated independently from the current level on the LIN pin. A voltage of less than the LIN pre-wake detection VLINL at the LIN pin activates the internal LIN receiver and starts the wake-up detection timer. If TXD is short-circuited to GND, it is possible to switch to Sleep mode via EN after t > tdom.  2018 Microchip Technology Inc.

DS50002820B-page 5 Document Outline Features General Description Package Types Block Diagram 1.0 Functional Description 1.1 Physical Layer Compatibility 1.2 Operating Modes FIGURE 1-1: Operating Modes TABLE 1-1: Operating Modes (Mode Pin Is Always Low) 1.2.1 Normal Mode 1.2.2 Silent Mode FIGURE 1-2: Switching to Silent mode 1.2.3 Sleep Mode FIGURE 1-3: Switching to Sleep Mode 1.2.4 Fail-Safe mode TABLE 1-2: Signaling in Fail-safe Mode 1.3 Wake-up Scenarios from Silent Mode or Sleep Mode 1.3.1 Remote Wake-up via LIN Bus 1.3.1.1 Remote Wake-up from Silent Mode FIGURE 1-4: LIN Wake-up from Silent Mode 1.3.1.2 Remote Wake-up from Sleep Mode FIGURE 1-5: LIN Wake-up from Sleep Mode 1.3.2 Local Wake-up via WKin Pin FIGURE 1-6: Local Wake-up via WKin pin from Sleep Mode FIGURE 1-7: Local Wake-up via WKin pin from Silent Mode 1.3.3 Local Wake-up via CL15 1.3.4 Wake-up Source Recognition TABLE 1-3: Signaling in Fail-Safe Mode 1.4 Behavior under Low Supply Voltage Conditions FIGURE 1-8: VCC and NRES versus VS (Ramp-up) for ATA663431 FIGURE 1-9: VCC and NRES versus VS (Ramp-down) for ATA663431 FIGURE 1-10: VCC and NRES versus VS (Ramp-up) for ATA663454 FIGURE 1-11: VCC and NRES versus VS (Ramp-Down) for ATA663454 1.5 Voltage Regulator FIGURE 1-12: VCC Voltage Regulator: Supply Voltage Ramp-up and Ramp-down FIGURE 1-13: Power Dissipation: Safe Operating Area: Regulator’s Output Current IVCC versus Supply Voltage VVS at Different Ambient Temperatures (RthvJA = 45 K/W assumed) 1.6 Watchdog FIGURE 1-14: Limp Home (LH) State Diagram 1.6.1 Typical Timing Sequence with RWDOSC = 51 kΩ EQUATION 1-1: FIGURE 1-15: Timing Sequence with RWDOSC = 51 kΩ 1.6.2 Worst-Case Calculation with RWDOSC = 51 kΩ EQUATION 1-2: TABLE 1-4: Typical Watchdog Timings 1.7 Pin Descriptions TABLE 1-5: Pin Description 1.7.1 Bus Data Output Pin (RXD) 1.7.2 Enable Input Pin (EN) 1.7.3 Undervoltage Reset Output Pin (NRES) 1.7.4 Bus Data Input/Output (TXD) 1.7.5 NTRIG Input Pin 1.7.6 Mode Input Pin (MODE) 1.7.7 WDOSC Output Pin 1.7.8 High-side Switch Pins (HSout, HSin) 1.7.9 Limp Home Watchdog Failure Output (LH) 1.7.10 CL15 Pin 1.7.11 Wake Input Pin (WKin) 1.7.12 Ground Pin (GND) 1.7.13 Bus Pin (LIN) 1.7.14 Supply Pin (VS) 1.7.15 Voltage Regulator Output Pin (VCC) Typical Application Circuit 2.0 Electrical Characteristics 2.1 Absolute Maximum Ratings† Electrical Characteristics FIGURE 2-1: Definition of Bus timing Characteristics Temperature Specifications 3.0 Packaging Information 3.1 Package Marking Information LIN SBC including LIN Transceiver, Voltage Regulator, Window Watchdog and High-Side Switch Appendix A: Revision History Revision A (November 2018) Revision B (November 2018) Product Identification System AMERICAS Corporate Office Atlanta Austin, TX Boston Chicago Dallas Detroit Houston, TX Indianapolis Los Angeles Raleigh, NC New York, NY San Jose, CA Canada - Toronto ASIA/PACIFIC Australia - Sydney China - Beijing China - Chengdu China - Chongqing China - Dongguan China - Guangzhou China - Hangzhou China - Hong Kong SAR China - Nanjing China - Qingdao China - Shanghai China - Shenyang China - Shenzhen China - Suzhou China - Wuhan China - Xian China - Xiamen China - Zhuhai ASIA/PACIFIC India - Bangalore India - New Delhi India - Pune Japan - Osaka Japan - Tokyo Korea - Daegu Korea - Seoul Malaysia - Kuala Lumpur Malaysia - Penang Philippines - Manila Singapore Taiwan - Hsin Chu Taiwan - Kaohsiung Taiwan - Taipei Thailand - Bangkok Vietnam - Ho Chi Minh EUROPE Austria - Wels Denmark - Copenhagen Finland - Espoo France - Paris Germany - Garching Germany - Haan Germany - Heilbronn Germany - Karlsruhe Germany - Munich Germany - Rosenheim Israel - Ra’anana Italy - Milan Italy - Padova Netherlands - Drunen Norway - Trondheim Poland - Warsaw Romania - Bucharest Spain - Madrid Sweden - Gothenberg Sweden - Stockholm UK - Wokingham Worldwide Sales and Service
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