Datasheet M95M04-DR (STMicroelectronics) - 2
| Manufacturer | STMicroelectronics |
| Description | 4-Mbit serial SPI bus EEPROM |
| Pages / Page | 46 / 2 — Contents. M95M04-DR. Description . 6. Memory organization . 8. Signal … |
| File Format / Size | PDF / 858 Kb |
| Document Language | English |
Contents. M95M04-DR. Description . 6. Memory organization . 8. Signal description . 9. Connecting to the SPI bus . 11
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Contents M95M04-DR Contents 1 Description . 6 2 Memory organization . 8 3 Signal description . 9
3.1 Serial data output (Q) . 9 3.2 Serial data input (D) . 9 3.3 Serial clock (C) . 9 3.4 Chip select (S) . 9 3.5 Hold (HOLD) . 9 3.6 Write protect (W) . 10 3.7 VCC supply voltage . 10 3.8 VSS ground . 10
4 Connecting to the SPI bus . 11
4.1 SPI modes . 12
5 Operating features . 13
5.1 Supply voltage (VCC) . 13 5.1.1 Operating supply voltage (VCC) . 13 5.1.2 Device reset . 13 5.1.3 Power-up conditions . 13 5.1.4 Power-down . 14 5.2 Active power and Standby power modes . 14 5.3 Hold condition . 14 5.4 Status register . 15 5.5 Data protection and protocol control . 15
6 Instructions . 16
6.1 Write enable (WREN) . 17 6.2 Write disable (WRDI) . 18 6.3 Read Status register (RDSR) . 19 6.3.1 WIP bit . 19 2/46 DS12179 Rev 1 Document Outline 1 Description Figure 1. Logic diagram Table 1. Signal names Figure 2. 8-pin package connections (top view) Figure 3. WLCSP connections Table 2. Signals vs. bump position 2 Memory organization Figure 4. Block diagram 3 Signal description 3.1 Serial data output (Q) 3.2 Serial data input (D) 3.3 Serial clock (C) 3.4 Chip select (S) 3.5 Hold (HOLD) 3.6 Write protect (W) 3.7 VCC supply voltage 3.8 VSS ground 4 Connecting to the SPI bus Figure 5. Bus master and memory devices on the SPI bus 4.1 SPI modes Figure 6. SPI modes supported 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) 5.1.2 Device reset 5.1.3 Power-up conditions 5.1.4 Power-down 5.2 Active power and Standby power modes 5.3 Hold condition Figure 7. Hold condition activation 5.4 Status register 5.5 Data protection and protocol control Table 3. Write-protected block size 6 Instructions Table 4. Instruction set Table 5. Significant bits within the address bytes 6.1 Write enable (WREN) Figure 8. Write enable (WREN) sequence 6.2 Write disable (WRDI) Figure 9. Write disable (WRDI) sequence 6.3 Read Status register (RDSR) Figure 10. Read Status register (RDSR) sequence 6.3.1 WIP bit 6.3.2 WEL bit 6.3.3 BP1, BP0 bits 6.3.4 SRWD bit Table 6. Status register format 6.4 Write Status register (WRSR) Figure 11. Write Status register (WRSR) sequence Table 7. Protection modes 6.5 Read from Memory array (READ) Figure 12. Read from Memory array (READ) sequence 6.6 Write to Memory array (WRITE) Figure 13. Byte Write (WRITE) sequence Figure 14. Page Write (WRITE) sequence 6.7 Read Identification page Figure 15. Read Identification page sequence 6.8 Write Identification page Figure 16. Write Identification page sequence 6.9 Read Lock status Figure 17. Read Lock status sequence 6.10 Lock ID Figure 18. Lock ID sequence 6.11 Error correction code (ECC x 4) and write cycling 7 Power-up and delivery state 7.1 Power-up state 7.2 Initial delivery state 8 Maximum ratings Table 8. Absolute maximum ratings 9 DC and AC parameters Table 9. Operating conditions (range R) Table 10. AC measurement conditions Figure 19. AC measurement I/O waveform Table 11. Cycling performance by groups of four bytes Table 12. Memory cell data retention Table 13. Capacitance Table 14. DC characteristics Table 15. AC characteristics Figure 20. Serial input timing Figure 21. Hold timing Figure 22. Serial output timing 10 Package information 10.1 SO8N package information Figure 23. SO8N outline Table 16. SO8N mechanical data Figure 24. SO8N recommended footprint 10.2 WLCSP8 package information Figure 25. WLCSP (with BSC) outline Table 17. WLCSP mechanical data Figure 26. WLCSP recommended footprint 10.3 TSSOP8 package information Figure 27. TSSOP8 outline Table 18. TSSOP8 mechanical data Figure 28. TSSOP8 recommended footprint 11 Ordering information 12 Revision history Table 19. Document revision history
Contents M95M04-DR Contents 1 Description . 6 2 Memory organization . 8 3 Signal description . 9
3.1 Serial data output (Q) . 9 3.2 Serial data input (D) . 9 3.3 Serial clock (C) . 9 3.4 Chip select (S) . 9 3.5 Hold (HOLD) . 9 3.6 Write protect (W) . 10 3.7 VCC supply voltage . 10 3.8 VSS ground . 10
4 Connecting to the SPI bus . 11
4.1 SPI modes . 12
5 Operating features . 13
5.1 Supply voltage (VCC) . 13 5.1.1 Operating supply voltage (VCC) . 13 5.1.2 Device reset . 13 5.1.3 Power-up conditions . 13 5.1.4 Power-down . 14 5.2 Active power and Standby power modes . 14 5.3 Hold condition . 14 5.4 Status register . 15 5.5 Data protection and protocol control . 15
6 Instructions . 16
6.1 Write enable (WREN) . 17 6.2 Write disable (WRDI) . 18 6.3 Read Status register (RDSR) . 19 6.3.1 WIP bit . 19 2/46 DS12179 Rev 1 Document Outline 1 Description Figure 1. Logic diagram Table 1. Signal names Figure 2. 8-pin package connections (top view) Figure 3. WLCSP connections Table 2. Signals vs. bump position 2 Memory organization Figure 4. Block diagram 3 Signal description 3.1 Serial data output (Q) 3.2 Serial data input (D) 3.3 Serial clock (C) 3.4 Chip select (S) 3.5 Hold (HOLD) 3.6 Write protect (W) 3.7 VCC supply voltage 3.8 VSS ground 4 Connecting to the SPI bus Figure 5. Bus master and memory devices on the SPI bus 4.1 SPI modes Figure 6. SPI modes supported 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) 5.1.2 Device reset 5.1.3 Power-up conditions 5.1.4 Power-down 5.2 Active power and Standby power modes 5.3 Hold condition Figure 7. Hold condition activation 5.4 Status register 5.5 Data protection and protocol control Table 3. Write-protected block size 6 Instructions Table 4. Instruction set Table 5. Significant bits within the address bytes 6.1 Write enable (WREN) Figure 8. Write enable (WREN) sequence 6.2 Write disable (WRDI) Figure 9. Write disable (WRDI) sequence 6.3 Read Status register (RDSR) Figure 10. Read Status register (RDSR) sequence 6.3.1 WIP bit 6.3.2 WEL bit 6.3.3 BP1, BP0 bits 6.3.4 SRWD bit Table 6. Status register format 6.4 Write Status register (WRSR) Figure 11. Write Status register (WRSR) sequence Table 7. Protection modes 6.5 Read from Memory array (READ) Figure 12. Read from Memory array (READ) sequence 6.6 Write to Memory array (WRITE) Figure 13. Byte Write (WRITE) sequence Figure 14. Page Write (WRITE) sequence 6.7 Read Identification page Figure 15. Read Identification page sequence 6.8 Write Identification page Figure 16. Write Identification page sequence 6.9 Read Lock status Figure 17. Read Lock status sequence 6.10 Lock ID Figure 18. Lock ID sequence 6.11 Error correction code (ECC x 4) and write cycling 7 Power-up and delivery state 7.1 Power-up state 7.2 Initial delivery state 8 Maximum ratings Table 8. Absolute maximum ratings 9 DC and AC parameters Table 9. Operating conditions (range R) Table 10. AC measurement conditions Figure 19. AC measurement I/O waveform Table 11. Cycling performance by groups of four bytes Table 12. Memory cell data retention Table 13. Capacitance Table 14. DC characteristics Table 15. AC characteristics Figure 20. Serial input timing Figure 21. Hold timing Figure 22. Serial output timing 10 Package information 10.1 SO8N package information Figure 23. SO8N outline Table 16. SO8N mechanical data Figure 24. SO8N recommended footprint 10.2 WLCSP8 package information Figure 25. WLCSP (with BSC) outline Table 17. WLCSP mechanical data Figure 26. WLCSP recommended footprint 10.3 TSSOP8 package information Figure 27. TSSOP8 outline Table 18. TSSOP8 mechanical data Figure 28. TSSOP8 recommended footprint 11 Ordering information 12 Revision history Table 19. Document revision history
