Datasheet SIC466, SiC467, SiC468, SiC469 (Vishay) - 8

SiC466, SiC467, SiC468, SiC469
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OUTPUT MONITORING AND PROTECTION FEATURES Output Over-Current Protection (OCP) Sequencing of Input / Output Supplies
SiC46x has cycle by cycle current limiting. The inductor SiC46x has no sequencing requirements on any of its valley current is monitored during LS FET turn-on period input / output (VIN, VDRV, VDD, VCIN, EN) supplies or enables. through RDS(on) sensing. After a pre-defined blanking time,
Enable
the valley current is compared with an internal threshold. If monitored current is higher than threshold, high side The SiC46x has an enable pin to turn the part on and off. MOSFET is kept off until the inductor current falls below Driving this pin high enables the device, while grounding it OCP threshold. turns it off. OCP is enabled immediately after V The SiC46x enable has a weak pull down to prevent DD passes UVLO rising threshold. unwanted turn on due to a floating GPIO. There are 3 settings for the valley current OCP namely 50 %, There are no sequencing requirements with respect to other 75 % and 100 %. The selection can be chosen by input / output supplies. connecting the ILIMIT pin either to VDD, float or GND.
Soft-Start
Connecting to VDD will select 100 % of the preset valley current OCP corresponding to the SiC46x being used. If the During soft start time period, inrush current is limited and the pin is floating, the valley current OCP is 75 %. Connecting output voltage is ramped gradually. The following control to GND, the valley current OCP is 50 %. scheme is implemented: Once the VDD voltage reaches the UVLO trip point, an internal “Soft start Reference” (SR) begins to ramp up. The OCP SR ramp rate is determined by the external soft start threshold capacitor. There is an internal 5 μA current source tied to the Iload soft start pin which charges the external soft start cap. I The internal SR signal is being used as a reference voltage inductor to the loop error amplifier (see functional block diagram). The control scheme guarantees that the output voltage during the soft start interval will ramp up coincidently with GH the SR signal. voltage. The speed of the internal soft start
Fig. 6 - Over-Current Protection Illustration
ramp can SiC46x soft-start time is adjustable by selecting a capacitor value from the following equation.
Output Undervoltage Protection (UVP)
C x 0.8 V UVP is implemented by monitoring output through V ext FB pin. SS time = ---------------- If the voltage level at V 5 μA FB goes below 0.16 V (VOUT is 20 % of VOUT set point) for more than 25 μs a UVP event is During soft-start period, OCP is activated. Short circuit recognized and both HS and LS MOSFETs are turned off. protection is not active until soft-start is complete. After a time-out period equal to 20 soft start cycles, the IC attempts to re-start by going through a soft start cycle. If the
Pre-Bias Start-Up
fault condition still exists, the above cycle will be repeated. In case of pre-bias startup, if the sensed voltage on FB is UVP is only active after the completion of soft-start higher than the internal soft-start ramp value, control logic sequence. prevents HS and LS FET from switching to avoid negative
Output Over Voltage Protection (OVP)
output voltage spike and excessive current sinking through LS FET. For OVP implementation, output is monitored through FB pin. After soft start, if the voltage level at FB is above 0.96 V (typ.) (VOUT is 120 % of VOUT set point), OVP is triggered with both the HS and LS MOSFETs turned off. Normal operation is resumed once FB voltage drops back to 0.96 V. OVP is active immediately after VDD passes UVLO level.
Over Temperature Protection (OTP)
SiC46x has internal thermal monitor block that turns off both HS and LS FETs when junction temperature is above 150 °C (typ). A hysteresis of 35 °C is implemented, so when junction temperature drops below 115 °C, the device restarts by initiating soft-start sequence again.
Fig. 7 - Pre-Bias Start-Up
S19-0911-Rev. E, 28-Oct-2019
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