Datasheet XDPS21071 (Infineon) - 5

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Forced Frequency Resonant Flyback controller Representative Block Diagram 2 Representative Block Diagram
Figure 3 shows a simplified top level block diagram of the IC functionality.

HV
XDPS21071 HV Startup-cell Bang-Bang Ctrl
Closed/Open
Startup-Cell
VVCCBBoff = 20.5 V
Driver
VVCCBBonAR/LM = 9 V
Vbulk Brown-out Protection
QM IHVBO = 0.443 mA D1
Vbulk Vbulk Brown-in measurement Protection Overtemperature
R I M HVBI = 1.15 mA
Detection
TJOTP = 130 °C
VCC Brown-in
& VCC
Protection
VVCCBI = 9.1 V
Protection HW Reset UVLO Modes
VVCCon = 20.5 V
Auto Restart Power Mode
VVCCoffx = 7.2 V / 9.6 V
Management Vout OV Latch Vout reflected Voltage Protection
ZCD
Mode
1 k
Measurement
VZCDOVP = 2.75 V
Soft-Start Open Loop Timer
tMFIOH = 31.3 ms
Frequency clamp Gate Driver FFR Mode PWM Frequency Law
fSW GD0
With ZVS Pulse Logic Generation
C2 VCSPK V V MFIO MFIOH = 2.41 V
PDC
VVDDP = 3.3 V VMFIO
Gate Driver
RMFIOPU GD1
Burst Mode Function Vcs_offset
MFIO C3 VMFIOBMEX1
BM Exit
C5 VMFIOBMWK on-phase
BM 2-point BM Ctrl Regulation
C6 off-phase VMFIOBMPA C7 V
BM Entry
MFIOBMEN
Cycle by Cycle Peak Current Ctrl
OCP1 CS tCSLEB V 1 k 10k CSPK 1 pF
Auto Restart 2nd Level Overcurrent Detection Input Detection
OCP2 tCSOCP2BL VCSOCP2 = 0.8 V VVDDP = 3.3 V IGPIOLPU
UART Parameter
GPIO
Communication Configuration Figure 3 Representative Block Diagram of XDPS21071
Data Sheet 5 Revision 2.0 2019-10-30