Datasheet ADAU1787 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Four ADC, Two DAC, Low Power Codec with Audio DSPs |
| Pages / Page | 280 / 6 — ADAU1787. Data Sheet. FUNCTIONAL BLOCK DIAGRAM. N KI CL. I/M. PVD. … |
| Revision | A |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
ADAU1787. Data Sheet. FUNCTIONAL BLOCK DIAGRAM. N KI CL. I/M. PVD. BCLK_0. MICROPHONE. MICBIAS0. FSYNC_0. MASTER. BIAS. LDO. CLK. CLOCK. MICBIAS1
Model Line for this Datasheet
Text Version of Document
ADAU1787 Data Sheet FUNCTIONAL BLOCK DIAGRAM N KI CL N D D I/M O _E D L G DD DD DD V AL A PVD T RE DV AV AV H IO CM X XT BCLK_0 MICROPHONE MICBIAS0 FSYNC_0 MASTER BIAS LDO CM CLK CLOCK MICBIAS1 GENERATOR GENERATOR OSCILATOR PLL BCLK_1 FSYNC_1 A ADC SAI_0 AIN0 PG SAI_0 SAI_0 HPOUTP0/ SAI_1 SAI_1 SAI_1 LOUTP0 A DAC ADC ADC ADC HP ADC HPOUTN0/ AIN1 PG DECIMATION LOUTN0 8kHz TO 4 SigmaDSP 16 FastDSP 16 DMIC DMIC 64 ASRCI ROUTE 768kHz 50 MIPs ADC INSTRUCTIONS HPOUTP1/ A OUTPUT SDSP FDSP ADC ASRCI ASRCI FDSP LOUTP1 AIN2 PG DAC HP SDSP HPOUTN1/ FDSP SDSP LOUTN1 A ADC PG AIN3 SAI_0 INPUT OUTPUT 4 ASYNCHRONOUS 4 4 ASYNCHRONOUS 4 SAI_1 ROUTE SAMPLE RATE ROUTE SAMPLE RATE CONVERTER ASRCI CONVERTER ASRCO DMIC_CLK0/ ROUTE ROUTE MP7 DMIC_CLK1/ DIGITAL I_0 16 I_1 MP8 MICROPHONE 16 8 16 16 SA SA DECIMATION DMIC01/ 8kHz TO MP9 DMIC 768kHz SERIAL AUDIO PORT 0 SERIAL AUDIO PORT 1 I2C OR SPI DMIC23/ OUTPUT MASTER OR SLAVE MASTER OR SLAVE CONTROL PORT MP10 ADAU1787 DMIC4_5 DMIC6_7 D D D 2 1 0 2 4 I 3 5 6 ND N N N P P _0 P P S K P P P S S L SO 11 PD G P1 M M M O P M AG AG DG /M 0/ 0/ AO 1/ 1/ R0/ M /SC /MI HP _0/M _1/M _1/M A T/M K_ K_ L _EN NC_ DAT AI NC_ AO AI ADD DR1/ SC SD OO Y A Y BCL S S BCL S SW DAT DAT AD F F LFB S ADAT S E S S NOTES 1. SAI_0 IS THE SERIAL AUDIO INTERFACE 0. 2. SAI_1 IS THE SERIAL AUDIO INTERFACE 1. 3. DMIC IS THE DIGITAL MICROPHONE. 4. ASRCI IS THE INPUT ASYNCHRONOUS SAMPLE RATE CONVERTER.
1
5. ASRCO IS THE OUTPUT ASYNCHRONOUS SAMPLE RATE CONVERTER.
00
6. FDSP IS FastDSP.
7-
7. SDSP IS SigmaDSP.
2012 Figure 1. Rev. A | Page 6 of 280 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1787 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Outputs Pop and Click Suppression DACs DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE Signal Processing Details Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC Bias Current Control DAC Bias Current Control DAC Low Power Modes PLL Bypass SigmaDSP Clock Speed Control Asynchronous Sample Rate Converters Low Power Modes CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/WB Subaddress Data Bytes SELF BOOT EEPROM Size CRC Delay Boot Time MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORTS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ADI VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HPF CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER ADC CHANNEL 2 VOLUME CONTROL REGISTER ADC CHANNEL 3 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBS REGISTER PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 2 GAIN CONTROL LSBS REGISTER PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 1 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER DAC CHANNEL 1 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER FSYNC_1 PIN CONTROLS REGISTER BCLK_1 PIN CONTROLS REGISTER SDATAO_1 PIN CONTROLS REGISTER SDATAI_1 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER SERIAL PORT 1 CONTROL 1 REGISTER SERIAL PORT 1 CONTROL 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER MP12 PIN CONTROL REGISTER SELFBOOT PIN CONTROLS REGISTER SW_EN PIN CONTROLS REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
1
5. ASRCO IS THE OUTPUT ASYNCHRONOUS SAMPLE RATE CONVERTER.
00
6. FDSP IS FastDSP.
7-
7. SDSP IS SigmaDSP.
2012 Figure 1. Rev. A | Page 6 of 280 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS ANALOG PERFORMANCE SPECIFICATIONS CRYSTAL AMPLIFIER SPECIFICATIONS DIGITAL INPUT AND OUTPUT SPECIFICATIONS POWER SUPPLY SPECIFICATIONS POWER-DOWN CURRENT TYPICAL POWER CONSUMPTION DIGITAL FILTERS DIGITAL TIMING SPECIFICATIONS Digital Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS SYSTEM BLOCK DIAGRAM THEORY OF OPERATION SYSTEM CLOCKING AND POWER-UP POWER-DOWN OPERATION AND OPTIONS EXAMPLE ADC TO DAC POWER-UP DVDD LDO REGULATOR CLOCK INITIALIZATION PLL Enabled Setup Control Port Access During Initialization PLL PLL Bypass Operation Input Clock Divider Integer Mode Fractional Mode MULTICHIP PHASE SYNCHRONIZATION CLOCK OUTPUT POWER SUPPLY SEQUENCING Power-Down Considerations SIGNAL ROUTING INPUT SIGNAL PATHS ANALOG INPUTS Phase Difference Various Signal Path ADAU1787 Input Impedance Analog Microphone Inputs Analog Line Inputs Precharging Input Capacitors Microphone Bias PGAs DIGITAL MICROPHONE INPUTS Digital Microphone Volume Control ADCs ADC Full-Scale Level Digital ADC Volume Control Filtering OUTPUT SIGNAL PATHS ANALOG OUTPUTS Headphone Output Line Outputs Pop and Click Suppression DACs DAC Full-Scale Level Digital DAC Volume Control and Filtering PDM OUTPUTS PDM Outputs Full-Scale Level PDM Outputs Volume Control and Filtering ASRCs INTERPOLATION AND DECIMATION BLOCKS SIGNAL LEVELS FastDSP CORE INSTRUCTIONS FILTER PRECISION FLAGS AND CONDITIONAL EXECUTION INPUT SOURCES POWER AND RUN CONTROL DATA MEMORY PARAMETERS PARAMETER BANK SWITCHING PARAMETER BANK COPYING PARAMETER MEMORY ACCESS FastDSP PARAMETER SAFELOAD SigmaDSP CORE Signal Processing Details Program Counter Watchdog Features Numeric Formats Numeric Format 5.23 Programming READ/WRITE DATA FORMATS SOFTWARE SAFELOAD FastDSP SAFELOAD PROGRAM RAM, PARAMETER RAM, AND DATA RAM PROGRAM RAM PARAMETER RAM DATA RAM POWER SAVING OPTIONS ADC Bias Current Control DAC Bias Current Control DAC Low Power Modes PLL Bypass SigmaDSP Clock Speed Control Asynchronous Sample Rate Converters Low Power Modes CONTROL PORT BURST MODE COMMUNICATION READING AND WRITING TO MEMORIES I2C PORT Addressing I2C Read and Write Operations SPI PORT R/WB Subaddress Data Bytes SELF BOOT EEPROM Size CRC Delay Boot Time MULTIPURPOSE PINS Interrupts Pin Controls SERIAL DATA PORTS APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS LAYOUT GROUNDING PCB STACKUP REGISTER SUMMARY REGISTER DETAILS ADI VENDOR ID REGISTER DEVICE ID REGISTERS REVISION CODE REGISTER ADC, DAC, HEADPHONE POWER CONTROLS REGISTER PLL, MICROPHONE BIAS, AND PGA POWER CONTROLS REGISTER DIGITAL MICROPHONE POWER CONTROLS REGISTER SERIAL PORT, PDM OUTPUT, AND DIGITAL MICROPHONE CLK POWER CONTROLS REGISTER DSP POWER CONTROLS REGISTER ASRC POWER CONTROLS REGISTER INTERPOLATOR POWER CONTROLS REGISTER DECIMATOR POWER CONTROLS REGISTER STATE RETENTION CONTROLS REGISTER CHIP POWER CONTROL REGISTER CLOCK CONTROL REGISTER PLL INPUT DIVIDER REGISTER PLL FEEDBACK INTEGER DIVIDER (LSBs REGISTER) PLL FEEDBACK INTEGER DIVIDER (MSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (LSBs REGISTER) PLL FRACTIONAL NUMERATOR VALUE (MSBs REGISTER) PLL FRACTIONAL DENOMINATOR (LSBs REGISTER) PLL FRACTIONAL DENOMINATOR (MSBs REGISTER) PLL UPDATE REGISTER ADC SAMPLE RATE CONTROL REGISTER ADC IBIAS CONTROLS REGISTER ADC HPF CONTROL REGISTER ADC MUTE AND COMPENSATION CONTROL REGISTER ANALOG INPUT PRECHARGE TIME REGISTER ADC CHANNEL MUTES REGISTER ADC CHANNEL 0 VOLUME CONTROL REGISTER ADC CHANNEL 1 VOLUME CONTROL REGISTER ADC CHANNEL 2 VOLUME CONTROL REGISTER ADC CHANNEL 3 VOLUME CONTROL REGISTER PGA CHANNEL 0 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 0 GAIN CONTROL LSBs REGISTER PGA CHANNEL 1 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 1 GAIN CONTROL LSBS REGISTER PGA CHANNEL 2 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 2 GAIN CONTROL LSBS REGISTER PGA CHANNEL 3 GAIN CONTROL MSBs, MUTE, BOOST, SLEW REGISTER PGA CHANNEL 3 GAIN CONTROL LSBs REGISTER PGA SLEW RATE AND GAIN LINK REGISTER MICROPHONE BIAS LEVEL AND CURRENT REGISTER DIGITAL MICROPHONE CLOCK RATE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 0 AND CHANNEL 1 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 AND CHANNEL 3 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 AND CHANNEL 5 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 AND CHANNEL 7 RATE, ORDER, MAPPING, AND EDGE CONTROL REGISTER DIGTIAL MICROPHONE VOLUME OPTIONS REGISTER DIGITAL MICROPHONE CHANNEL MUTE CONTROLS REGISTER DIGITAL MICROPHONE CHANNEL 0 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 1 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 2 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 3 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 4 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 5 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 6 VOLUME CONTROL REGISTER DIGITAL MICROPHONE CHANNEL 7 VOLUME CONTROL REGISTER DAC SAMPLE RATE, FILTERING, AND POWER CONTROLS REGISTER DAC VOLUME LINK, HIGH-PASS FILTER (HPF), AND MUTE CONTROLS REGISTER DAC CHANNEL 0 VOLUME REGISTER DAC CHANNEL 1 VOLUME REGISTER DAC CHANNEL 0 ROUTING REGISTER DAC CHANNEL 1 ROUTING REGISTER HEADPHONE CONTROL REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER FAST TO SLOW DECIMATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER FAST TO SLOW DECIMATOR CHANNEL 0 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 1 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 2 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 3 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 4 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 5 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 6 INPUT ROUTING REGISTER FAST TO SLOW DECIMATOR CHANNEL 7 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 0 AND CHANNEL 1 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 2 AND CHANNEL 3 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 4 AND CHANNEL 5 REGISTER SLOW TO FAST INTERPOLATOR SAMPLE RATES CHANNEL 6 AND CHANNEL 7 REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 0 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 1 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 2 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 3 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 4 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 5 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 6 INPUT ROUTING REGISTER SLOW TO FAST INTERPOLATOR CHANNEL 7 INPUT ROUTING REGISTER INPUT ASRC CONTROL, SOURCE, AND RATE SELECTION REGISTER INPUT ASRC CHANNEL 0 AND CHANNEL 1 INPUT ROUTING REGISTER INPUT ASRC CHANNEL 2 AND CHANNEL 3 INPUT ROUTING REGISTER OUTPUT ASRC CONTROL REGISTER OUTPUT ASRC CHANNEL 0 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 1 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 2 INPUT ROUTING REGISTER OUTPUT ASRC CHANNEL 3 INPUT ROUTING REGISTER FastDSP RUN REGISTER FastDSP CURRENT BANK AND BANK RAMPING CONTROLS REGISTER FastDSP BANK RAMPING STOP POINT REGISTER FastDSP BANK COPYING REGISTER FastDSP FRAME RATE SOURCE REGISTER FastDSP FIXED RATE DIVISION MSBs REGISTER FastDSP FIXED RATE DIVISION LSBs REGISTER FastDSP MODULO N COUNTER FOR LOWER RATE CONDITIONAL EXECUTION REGISTER FastDSP GENERIC CONDITIONAL EXECUTION REGISTERS FastDSP SAFELOAD ADDRESS REGISTER FastDSP SAFELOAD PARAMETER 0 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 1 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 2 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 3 VALUE REGISTERS FastDSP SAFELOAD PARAMETER 4 VALUE REGISTERS FastDSP SAFELOAD UPDATE REGISTER SigmaDSP FRAME RATE SOURCE SELECT REGISTER SigmaDSP RUN REGISTER SigmaDSP WATCHDOG CONTROLS REGISTER SigmaDSP WATCHDOG VALUE REGISTERS SigmaDSP MODULO DATA MEMORY START POSITION REGISTERS SigmaDSP FIXED FRAME RATE DIVISOR REGISTERS SigmaDSP SET INTERRUPTS REGISTER MULTIPURPOSE PIN 0 AND PIN 1 MODE SELECT REGISTER MULTIPURPOSE PIN 2 AND PIN 3 MODE SELECT REGISTER MULTIPURPOSE PIN 4 AND PIN 5 MODE SELECT REGISTER MULTIPURPOSE PIN 6 AND PIN 7 MODE SELECT REGISTER MULTIPURPOSE PIN 8 AND PIN 9 MODE SELECT REGISTER MULTIPURPOSE PIN 10 AND PIN 11 MODE SELECT REGISTER GENERAL-PURPOSE INPUT DEBOUNCE CONTROL AND MASTER CLOCK OUTPUT RATE SELECTION REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 0 TO PIN 7 REGISTER GENERAL-PURPOSE OUTPUTS CONTROL PIN 8 TO PIN 10 REGISTER FSYNC_0 PIN CONTROLS REGISTER BCLK_0 PIN CONTROLS REGISTER SDATAO_0 PIN CONTROL REGISTER SDATAI_0 PIN CONTROLS REGISTER FSYNC_1 PIN CONTROLS REGISTER BCLK_1 PIN CONTROLS REGISTER SDATAO_1 PIN CONTROLS REGISTER SDATAI_1 PIN CONTROLS REGISTER DMIC_CLK0 PIN CONTROLS REGISTER DMIC_CLK1 PIN CONTROLS REGISTER DMIC01 PIN CONTROLS REGISTER DMIC23 PIN CONTROLS REGISTER SDA/MISO PIN CONTROLS REGISTER IRQ SIGNALING AND CLEARING REGISTER IRQ1 MASKING REGISTERS IRQ2 MASKING REGISTERS CHIP RESETS REGISTER FastDSP CURRENT LAMBDA REGISTER CHIP STATUS 1 REGISTER CHIP STATUS 2 REGISTER GENERAL-PURPOSE INPUT READ 0 TO INPUT READ 7 REGISTER GENERAL-PURPOSE INPUT READ 8 TO INPUT READ 10 REGISTER DSP STATUS REGISTER IRQ1 STATUS 1 REGISTER IRQ1 STATUS 2 REGISTER IRQ1 STATUS 3 REGISTER IRQ2 STATUS 1 REGISTER IRQ2 STATUS 2 REGISTER IRQ2 STATUS 3 REGISTER SERIAL PORT 0 CONTROL 1 REGISTER SERIAL PORT 0 CONTROL 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 0 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 0 OUTPUT ROUTING SLOT 15 REGISTER SERIAL PORT 1 CONTROL 1 REGISTER SERIAL PORT 1 CONTROL 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 0 (LEFT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 1 (RIGHT REGISTER) SERIAL PORT 1 OUTPUT ROUTING SLOT 2 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 3 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 4 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 5 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 6 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 7 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 8 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 9 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 10 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 11 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 12 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 13 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 14 REGISTER SERIAL PORT 1 OUTPUT ROUTING SLOT 15 REGISTER MP12 PIN CONTROL REGISTER SELFBOOT PIN CONTROLS REGISTER SW_EN PIN CONTROLS REGISTER PDM SAMPLE RATE AND FILTERING CONTROL REGISTER PDM MUTING, HIGH-PASS, AND VOLUME OPTIONS REGISTER PDM OUTPUT CHANNEL 0 VOLUME REGISTER PDM OUTPUT CHANNEL 1 VOLUME REGISTER PDM OUTPUT CHANNEL 0 ROUTING REGISTER PDM OUTPUT CHANNEL 1 ROUTING REGISTER OUTLINE DIMENSIONS ORDERING GUIDE
