Datasheet ADT7470 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | Temperature Sensor Hub and Fan Controller |
| Pages / Page | 40 / 4 — ADT7470. Data Sheet. SERIAL BUS TIMING SPECIFICATIONS. Table 2. … |
| Revision | E |
| File Format / Size | PDF / 587 Kb |
| Document Language | English |
ADT7470. Data Sheet. SERIAL BUS TIMING SPECIFICATIONS. Table 2. Parameter1, 2, 3, 4, 5 M. Typ. Max. Unit. Test. Conditions/Comments. LOW
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ADT7470 Data Sheet SERIAL BUS TIMING SPECIFICATIONS Table 2. Parameter1, 2, 3, 4, 5 M in Typ Max Unit Test Conditions/Comments
SERIAL BUS TIMING Clock Frequency, fSCLK 400 kHz See Figure 2 Glitch Immunity, tSW 50 ns See Figure 2 Bus Free Time, tBUF 1.3 μs See Figure 2 Start Setup Time, tSU;STA 600 ns See Figure 2 Start Hold Time, tHD;STA 600 ns See Figure 2 SCL Low Time, tLOW 1.3 μs See Figure 2 SCL High Time, tHIGH 0.6 μs See Figure 2 SCL, SDA Rise Time, tr 300 ns See Figure 2 SCL, SDA Fall Time, tf 300 ns See Figure 2 Data Setup Time, tSU;DAT 100 ns See Figure 2 Detect Clock Low Timeout, tTIMEOUT 25 28 31 ms Can be optionally disabled, via Configuration Register 1 (see Table 6) 1 VDD should never be floated in the presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD. 2 All voltages are measured with respect to GND, unless otherwise specified. 3 Typical values are at %A = 25°C and represent the most likely parametric norm. 4 Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. 5 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
tR tF t t LOW HD;STA SCL tHIGH tSU;STA tSU;STO tHD;STA tHD;DAT tSU;DAT SDA tBUF P S S P
04684-0-002 Figure 2. Serial Bus Timing Diagram Rev. E | Page 4 of 40 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Serial Bus Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Functional Description General Description ADT7470 Monitoring Cycle Configuration Register 1 (Address 0x40) Configuration Register 2 (Address 0x74) ID Registers General-Purpose I/O Pins (Open Drain) SMBus/I2C Serial Interface Address Selection Serial Bus Protocol Write Operations Send Byte Write Byte Read Operations Receive Byte Alert Response Address SMBus Timeout Temperature Measurement Using TMP05/TMP06 Measuring Temperature TMP05/TMP06 Decoder Temperature ReadBack By the Host Temperature Data Format Temperature Measurement Limits Thermal Zones for Automatic Fan Control Thermal Zone TMIN Limit and Status Registers Limit Values Temperature Limits Fan Speed Limits Out-of-Limit Comparisons Status Registers SMBALERT Interrupt Handling SMBALERT Interrupts Masking Interrupt Sources Enabling the SMBALERT Interrupt Output Fan Drive Using PWM Control High Frequency Fan Drive Low Frequency Fan Drive Setting the Fan Drive Frequency Inverted PWM Output Fan Full Speed Function Fan Speed Measurement Tach Inputs Pulse Stretching Disabling Tach measurement Fan Speed Measurement Fan Speed Measurement Registers Reading Fan Speed from the ADT7470 Fan Tach Limit Registers Fan Speed Measurement Rate Calculating Fan Speed and Tachometer Limits Fan Pulses per Revolution Manual Fan Speed Control Setting the PWM Duty Cycle Example 1: For a PWM Duty Cycle of 50% Example 2: For a PWM Duty Cycle of 33% Automatic Fan Speed Control PWM Min Duty Cycle Example: For a PWM Min Duty Cycle of 30% PWN Max Duty Cycle PWM Current Duty Cycle Register Map Detailed Register Descriptions Outline Dimensions Ordering Guide
ADT7470 Data Sheet SERIAL BUS TIMING SPECIFICATIONS Table 2. Parameter1, 2, 3, 4, 5 M in Typ Max Unit Test Conditions/Comments
SERIAL BUS TIMING Clock Frequency, fSCLK 400 kHz See Figure 2 Glitch Immunity, tSW 50 ns See Figure 2 Bus Free Time, tBUF 1.3 μs See Figure 2 Start Setup Time, tSU;STA 600 ns See Figure 2 Start Hold Time, tHD;STA 600 ns See Figure 2 SCL Low Time, tLOW 1.3 μs See Figure 2 SCL High Time, tHIGH 0.6 μs See Figure 2 SCL, SDA Rise Time, tr 300 ns See Figure 2 SCL, SDA Fall Time, tf 300 ns See Figure 2 Data Setup Time, tSU;DAT 100 ns See Figure 2 Detect Clock Low Timeout, tTIMEOUT 25 28 31 ms Can be optionally disabled, via Configuration Register 1 (see Table 6) 1 VDD should never be floated in the presence of SCL/SDA activity. Charge injection can be sufficient to induce approximately 0.6 V on VDD. 2 All voltages are measured with respect to GND, unless otherwise specified. 3 Typical values are at %A = 25°C and represent the most likely parametric norm. 4 Logic inputs accept input high voltages up to 5 V even when the device is operating at supply voltages below 5 V. 5 Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
tR tF t t LOW HD;STA SCL tHIGH tSU;STA tSU;STO tHD;STA tHD;DAT tSU;DAT SDA tBUF P S S P
04684-0-002 Figure 2. Serial Bus Timing Diagram Rev. E | Page 4 of 40 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Serial Bus Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Functional Description General Description ADT7470 Monitoring Cycle Configuration Register 1 (Address 0x40) Configuration Register 2 (Address 0x74) ID Registers General-Purpose I/O Pins (Open Drain) SMBus/I2C Serial Interface Address Selection Serial Bus Protocol Write Operations Send Byte Write Byte Read Operations Receive Byte Alert Response Address SMBus Timeout Temperature Measurement Using TMP05/TMP06 Measuring Temperature TMP05/TMP06 Decoder Temperature ReadBack By the Host Temperature Data Format Temperature Measurement Limits Thermal Zones for Automatic Fan Control Thermal Zone TMIN Limit and Status Registers Limit Values Temperature Limits Fan Speed Limits Out-of-Limit Comparisons Status Registers SMBALERT Interrupt Handling SMBALERT Interrupts Masking Interrupt Sources Enabling the SMBALERT Interrupt Output Fan Drive Using PWM Control High Frequency Fan Drive Low Frequency Fan Drive Setting the Fan Drive Frequency Inverted PWM Output Fan Full Speed Function Fan Speed Measurement Tach Inputs Pulse Stretching Disabling Tach measurement Fan Speed Measurement Fan Speed Measurement Registers Reading Fan Speed from the ADT7470 Fan Tach Limit Registers Fan Speed Measurement Rate Calculating Fan Speed and Tachometer Limits Fan Pulses per Revolution Manual Fan Speed Control Setting the PWM Duty Cycle Example 1: For a PWM Duty Cycle of 50% Example 2: For a PWM Duty Cycle of 33% Automatic Fan Speed Control PWM Min Duty Cycle Example: For a PWM Min Duty Cycle of 30% PWN Max Duty Cycle PWM Current Duty Cycle Register Map Detailed Register Descriptions Outline Dimensions Ordering Guide
