Datasheet KSZ8462HLI, KSZ8462FHLI (Microchip) - 2

KSZ8462HLI/FHLI
• Grandmaster, Master, Slave, Ordinary Clock (OC) • Energy Detect Power-Down (EDPD), which Dis- Support ables the PHY Transceiver when Cables are • IEEE1588v2 PTP Multicast and Unicast Frame Removed Support • Wake-on-LAN Supported with Configurable • Transports of PTP Over IPv4/IPv6 UDP and IEEE Packet Control 802.3 Ethernet • Dynamic Clock Tree Control to Reduce Clocking • Delay Request-Response and Peer Delay Mech- in Areas Not in Use anism • Power Consumption Less than 0.5W • Ingress/Egress Packet Time Stamp Capture/
Additional Features
Recording and Checksum Update • Single 25 MHz ±50 ppm Reference Clock • Correction Field Update with Residence Time and Requirement Link Delay • Comprehensive Programmable Two LED Indica- • IEEE1588v2 PTP Packet Filtering Unit to Reduce tors Support for Link, Activity, Full-/Half-Duplex Host Processor Overhead and 10/100 Speed • A 64-bit Adjustable System Precision Clock • LED Pins Directly Controllable • Twelve Trigger Output Units and Twelve Time • Industrial Temperature Range: –40°C to +85°C Stamp Input Units Available for Flexible • 64-Pin (10 mm x 10 mm) Lead Free (RoHS) IEEE1588v2 Control of Seven Programmable GPIO[6:0] Pins Synchronized to the Precision LQFP Package Time Clock
Applications
• GPIO Pin Usage for 1 PPS Generation, Fre- • Industrial Ethernet Applications that Employ IEEE quency Generator, Control Bit Streams, Event 802.3-Compliant MACs. (Ethernet/IP, Profinet, Monitoring, Precision Pulse Generation, Complex MODBUS TCP, etc) Waveform Generation • Real-Time Ethernet Networks Requiring Sub-
Host Interface
Microsecond Synchronization over Standard • Selectable 8- or 16-bit Wide Interface Ethernet • Supports Big- and Little-Endian Processors • IEC 61850 Networks Supporting Power Substa- tion Automation • Indirect Data Bus for Data, Address and Byte Enable to Access any I/O Registers and RX/TX • Networked Measurement and Control Systems FIFO Buffers • Industrial Automation and Motion Control Sys- • Large Internal Memory with 12Kbyte for RX FIFO tems and 6Kbytes for TX FIFO • Test and Measurement Equipment • Programmable Low, High, and Overrun Water- mark for Flow Control in RX FIFO • Efficient Architecture Design with Configurable Host Interrupt Schemes to Minimize Host CPU Overhead and Utilization • Queue Management Unit (QMU) Supervises Data Transfers Across This Interface
Power and Power Management
• Single 3.3V Power Supply with Optional VDD I/O for 1.8V, 2.5V, or 3.3V • Integrated Low Voltage (~1.3V) Low-Noise Regu- lator (LDO) Output for Digital and Analog Core Power • Supports IEEE P802.3az™ Energy Efficient Ethernet (EEE) to Reduce Power Consumption in Transceivers in LPI State • Full-Chip Hardware or Software Power-Down (All Registers Value are Not Saved and Strap-In Value will Re-Strap After Releasing the Power-Down) DS00002641A-page 2

 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Terms and Conditions 1.2 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Direction Terminology 3.2 Physical (PHY) Block 3.3 Media Access Controller (MAC) Block 3.4 Switch Block 3.5 Queue Management Unit (QMU) 3.6 IEEE 1588 Precision Time Protocol (PTP) Block 3.7 General Purpose and IEEE 1588 Input/Output (GPIO) 3.8 Using the GPIO Pins with the Trigger Output Units 3.9 Using the GPIO Pins with the Time Stamp Input Units 3.10 Device Clocks 3.11 Power 3.12 Power Management 3.13 Interfaces 4.0 Register Descriptions 4.1 Register Map of CPU Accessible I/O Registers 4.2 Register Bit Definitions 4.3 Management Information Base (MIB) Counters 4.4 Static MAC Address Table 4.5 Dynamic MAC Address Table 4.6 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Host Interface Read/Write Timing 7.2 Auto-Negotiation Timing 7.3 Trigger Output Unit and Time Stamp Input Unit Timing 7.4 Serial EEPROM Interface Timing 7.5 Reset and Power Sequence Timing 7.6 Reset Circuit Guidelines 8.0 Reference Circuit: LED Strap-In Pins 9.0 Reference Clock: Connection and Selection 10.0 Selection of Isolation Transformers 11.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service