Datasheet KSZ8842-16M, KSZ8842-32M (Microchip) - 8
| Manufacturer | Microchip |
| Description | Two-Port Ethernet Switch with Non-PCI Interface |
| Pages / Page | 132 / 8 — KSZ8842-16M/-32M. TABLE 2-1:. PIN DESCRIPTION FOR KSZ8842-16MQL/MVL … |
| File Format / Size | PDF / 3.0 Mb |
| Document Language | English |
KSZ8842-16M/-32M. TABLE 2-1:. PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT) (CONTINUED). Pin. Pin Name. Type. Description. Number
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KSZ8842-16M/-32M TABLE 2-1: PIN DESCRIPTION FOR KSZ8842-16MQL/MVL (8-/16-BIT) (CONTINUED) Pin Pin Name Type Description Number
Bus Interface Clock Local bus clock for synchronous bus systems. Maximum frequency is 12 BCLK IPD 50 MHz. This pin should be tied Low or unconnected if it is in asynchronous mode. 13 NC IPU No connect. 14 NC OPU No connect. Synchronous Ready Not Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend accesses. 15 SRDYN OPU For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8842M drives this pin low to signal wait states. Interrupt 16 INTRN OPD Active Low signal to host CPU to indicate an interrupt status bit is set, this pin needs an external 4.7 kΩ pull-up resistor. Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 17 LDEVN OPD decode to the KSZ8842M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not 18 RDN IPD Asynchronous read strobe, active-low. 19 EECS OPU EEPROM Chip Select Asynchronous Ready ARDY may be used when interfacing asynchronous buses to extend bus 20 ARDY OPD access cycles. It is asynchronous to the host CPU or bus clock. This pin needs an external 4.7 kΩ pull-up resistor. Cycle Not For VLBus-like mode cycle signal; this pin follows the addressing cycle 21 CYCLEN IPD to signal the command cycle. For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write cycles. Port 2 LED indicator 22 P2LED3 OPD See the description in pins 6, 7, and 8. 23 DGND GND Digital IO ground. 1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. Note: Internally generated power voltage. Do not connect an external 24 VDDCO P power supply to this pin. This pin is used for connecting external filter (Ferrite bead and capacitors). It is recommended this pin should be con- nected to 3.3V power rail by a 100Ω resistor for the internal LDO appli- cation. VLBus-like Mode Pull-down or float: Bus interface is configured for synchronous mode. 25 VLBUSN IPD Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or EISA-like burst mode. EEPROM Enable 26 EEEN IPD EEPROM is enabled and connected when this pin is pulled up. EEPROM is disabled when this pin is pulled down or no connect. DS00003459A-page 8
2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
Bus Interface Clock Local bus clock for synchronous bus systems. Maximum frequency is 12 BCLK IPD 50 MHz. This pin should be tied Low or unconnected if it is in asynchronous mode. 13 NC IPU No connect. 14 NC OPU No connect. Synchronous Ready Not Ready signal to interface with synchronous bus for both EISA-like and VLBus-like extend accesses. 15 SRDYN OPU For VLBus-like mode, the falling edge of this signal indicates ready. This signal is synchronous to the bus clock signal BCLK. For burst mode (32-bit interface only), the KSZ8842M drives this pin low to signal wait states. Interrupt 16 INTRN OPD Active Low signal to host CPU to indicate an interrupt status bit is set, this pin needs an external 4.7 kΩ pull-up resistor. Local Device Not Active Low output signal, asserted when AEN is Low and A15-A4 17 LDEVN OPD decode to the KSZ8842M address programmed into the high byte of the base address register. LDEVN is a combinational decode of the Address and AEN signal. Read Strobe Not 18 RDN IPD Asynchronous read strobe, active-low. 19 EECS OPU EEPROM Chip Select Asynchronous Ready ARDY may be used when interfacing asynchronous buses to extend bus 20 ARDY OPD access cycles. It is asynchronous to the host CPU or bus clock. This pin needs an external 4.7 kΩ pull-up resistor. Cycle Not For VLBus-like mode cycle signal; this pin follows the addressing cycle 21 CYCLEN IPD to signal the command cycle. For burst mode (32-bit interface only), this pin stays High for read cycles and Low for write cycles. Port 2 LED indicator 22 P2LED3 OPD See the description in pins 6, 7, and 8. 23 DGND GND Digital IO ground. 1.2V digital core voltage output (internal 1.2V LDO power supply output), this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. Note: Internally generated power voltage. Do not connect an external 24 VDDCO P power supply to this pin. This pin is used for connecting external filter (Ferrite bead and capacitors). It is recommended this pin should be con- nected to 3.3V power rail by a 100Ω resistor for the internal LDO appli- cation. VLBus-like Mode Pull-down or float: Bus interface is configured for synchronous mode. 25 VLBUSN IPD Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous mode or EISA-like burst mode. EEPROM Enable 26 EEEN IPD EEPROM is enabled and connected when this pin is pulled up. EEPROM is disabled when this pin is pulled down or no connect. DS00003459A-page 8
2020 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Functional Overview: Physical Layer Transceiver 3.2 Functional Overview: MAC and Switch 3.3 Bus Interface Unit (BIU) 3.4 Queue Management Unit (QMU) 3.5 Advanced Switch Functions 3.6 IEEE 802.1Q VLAN Support 3.7 QoS Priority Support 3.8 Rate-Limiting Support 3.9 Loopback Support 4.0 Register Descriptions 4.1 CPU Interface I/O Registers 4.2 Register Map: MAC and PHY 4.3 Type-of-Service (TOS) Priority Control Registers 4.4 Management Information Base (MIB) Counters 4.5 Static MAC Address Table 4.6 Dynamic MAC Address Table 4.7 VLAN Table 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 Asynchronous Timing without using Address Strobe (ADSN = 0) 7.2 Asynchronous Timing using Address Strobe (ADSN) 7.3 Asynchronous Timing using DATACSN (KSZ8842-32MQL/MVL Only) 7.4 Address Latching Timing for All Modes 7.5 Synchronous Timing in Burst Write (VLBUSN = 1) 7.6 Synchronous Timing in Burst Read (VLBUSN = 1) 7.7 Synchronous Write Timing (VLBUSN = 0) 7.8 Synchronous Read Timing (VLBUSN = 0) 7.9 EEPROM Timing 7.10 Auto-Negotiation Timing 7.11 Reset Timing 8.0 Selection of Isolation Transformers 9.0 Package Outline 9.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
