Datasheet KSZ8895MLUB (Microchip) - 10

KSZ8895MLUB TABLE 2-1: SIGNALS - KSZ8895MLUB (CONTINUED) Type, Pin Pin Note Port Pin Function Number Name 2-1
76 GNDD GND — Digital ground. 77 VDDIO P — 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry. Port 5 Switch MII receive clock: 78 SMRXC I/O — Input: SW5-MII MAC mode. Output: SW5-MII PHY mode. 79 SMRXDV IPD/O — Switch MII receive data valid. Port 5 Switch MII receive bit 3. Strap option: 80 SMRXD3 IPD/O — PD (default) = Disable Switch SW5-MII full-duplex flow control PU = Enable Switch SW5-MII full-duplex flow control. Port 5 Switch MII receive bit 2. Strap option: 81 SMRXD2 IPD/O — PD (default) = Switch SW5-MII in full-duplex mode; PU = Switch SW5-MII in half-duplex mode. Port 5 Switch MII receive bit 1. Strap option: 82 SMRXD1 IPD/O — PD (default) = Port 5 Switch SW5-MII in 100 Mbps mode; SW5- TMII in 200 Mbps mode. PU = Switch SW5-MII in 10 Mbps mode. Port 5 Switch MII receive bit 0. Strap option: LED mode PD (default) = mode 0; PU = mode 1. See “Register 11.” Mode 0, link at 100/Full LEDx[2,1,0]=0,0,0 100/Half LEDx[2,1,0]=0,1,0 10/Full LEDx[2,1,0]=0,0,1 10/Half LEDx[2,1,0]=0,1,1 Mode 1, link at 83 SMRXD0 IPD/O — 100/Full LEDx[2,1,0]=0,1,0 100/Half LEDx[2,1,0]=0,1,1 10/Full LEDx[2,1,0]=1,0,0 10/Half LEDx[2,1,0]=1,0,1 —
Mode 0 Mode 1
LEDx_2 Link/Activity 100Link/Activity LEDx_1 Full-Duplex/Col 10Link/Activity LEDx_0 Speed Full-Duplex Port 5 Switch MII collision detect: 84 SCOL IPD/O — Input: SW5-MII MAC modes. Output: SW5-MII PHY modes. Port 5 Switch MII modes carrier sense: 85 SCRS IPD/O — Input: SW5-MII MAC modes. Output: SW5-MII PHY modes. DS00002680A-page 10

 2018 Microchip Technology Inc. Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service